José Silva-Martínez

157 papers A 1C 11Misc 2Journal 94Unranked 48
YearRankTypeTitle / Venue / Authors
2022 J jnl
An Interference-Tolerant Synchronization Scheme for Wireless Communication Systems Based on Direct Sequence Spread Spectrum.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jian Shao, Aydin Ilker Karsilayan, Christopher T. Rodenbeck, José Silva-Martínez
2021 J jnl
Recent Advances on Linear Low-Dropout Regulators.
IEEE Trans. Circuits Syst. II Express Briefs
José Silva-Martínez, Xiaosen Liu, Dadian Zhou
2020 J jnl
A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier.
IEEE Trans. Circuits Syst.
Chulhyun Park, Tao Chen, Kyoohyun Noh, Dadian Zhou, Suraj Prakash, Mohammadhossein Naderi Alizadeh, Aydin I. Karsilayan, Degang Chen, Randall L. Geiger, José Silva-Martínez
2020 J jnl
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator.
IEEE J. Solid State Circuits
Dadian Zhou, Junning Jiang, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2020 C conf
A 3 to 6 GHz Highly Linear I-Channel Receiver with over +3.0 dBm In-Band P1dB and 200 MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications.
ISCAS
Jusung Kim, Junning Jiang, José Silva-Martínez, Aydin Ilker Karsilayan
2020 — conf
A Blind Calibration Scheme for Switched-Capacitor Pipeline Analog-to-Digital Converters.
LASCAS
Juan A. Bozzo, Angel Abusleme, José Silva-Martínez
2020 J jnl
A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test.
IEEE Trans. Instrum. Meas.
Tao Chen, Chulhyun Park, Hao Meng, Dadian Zhou, José Silva-Martínez, Randall L. Geiger, Degang Chen
2020 J jnl
An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference.
IEEE Trans. Circuits Syst.
Jian Shao, Aydin Ilker Karsilayan, Christopher T. Rodenbeck, José Silva-Martínez
2020 J jnl
An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method.
IEEE Trans. Instrum. Meas.
Tao Chen, Chulhyun Park, Shravan K. Chaganti, José Silva-Martínez, Randall L. Geiger, Degang Chen
2020 J jnl
MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems.
IEEE Trans. Circuits Syst.
José Silva-Martínez, José G. Delgado-Frias
2019 J jnl
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang, Chulhyun Park, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2019 J jnl
A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez
2019 J jnl
A 3-6-GHz Highly Linear I-Channel Receiver With Over +3.0-dBm In-Band P
IEEE Trans. Circuits Syst. I Regul. Pap.
Junning Jiang, Jusung Kim, Aydin Ilker Karsilayan, José Silva-Martínez
2019 — conf
Efficient Broadband Class AB Amplifier.
MWSCAS
José Silva-Martínez, Tanwei Yan, Junning Jiang, Jian Shao
2019 J jnl
When Less Is More ... Few Bit ADCs in RF Systems.
IEEE Access
Christopher T. Rodenbeck, Matthew Martinez, Joshua B. Beun, José Silva-Martínez, Aydin Ilker Karsilayan, Robert Liechty
2018 J jnl
A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications.
IEEE Trans. Very Large Scale Integr. Syst.
John S. Mincey, Eric C. Su, José Silva-Martínez, Christopher T. Rodenbeck
2018 J jnl
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs.
IEEE J. Solid State Circuits
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2018 J jnl
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez
2018 — conf
Low noise RF quadrature VCO using tail-switch network-based coupling in 40 nm CMOS.
CICC
Venkatraman Natarajan, Mohammad H. Naderi, José Silva-Martínez
2018 J jnl
Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohammad H. Naderi, Suraj Prakash, José Silva-Martínez
2017 C conf
A 13bit 200MS/S pipeline ADC with current-mode MDACs.
ISCAS
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, José Silva-Martínez
2017 — conf
A 200MSPS time-interleaved 12-bit ADC system with digital calibration.
MWSCAS
Aditya Bommireddipalli, Dadian Zhou, Claudio Talarico, José Silva-Martínez, Aydin I. Karsilayan
2017 J jnl
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS.
IEEE J. Solid State Circuits
Alexander Edward, Qiyuan Liu, Carlos Briseno-Vidrios, Martin Kinyua, Eric G. Soenen, Aydin Ilker Karsilayan, José Silva-Martínez
2017 J jnl
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage.
IEEE J. Solid State Circuits
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
2017 J jnl
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques.
IEEE J. Solid State Circuits
Qiyuan Liu, Alexander Edward, Martin Kinyua, Eric G. Soenen, José Silva-Martínez
2017 — conf
Algorithmic-pipelined ADC with a modified residue curve for better linearity.
MWSCAS
Mohammad H. Naderi, José Silva-Martínez
2017 J jnl
Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jun Zhou, Amir Tofighi Zavareh, Robin Gupta, Liang Liu, Zhongfeng Wang, Brian M. Sadler, José Silva-Martínez, Sebastian Hoyos
2017 — conf
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications.
MWSCAS
Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Negar Rashidi, José Silva-Martínez
2017 J jnl
Low-Power G
IEEE Trans. Circuits Syst. II Express Briefs
John S. Mincey, Carlos Briseno-Vidrios, José Silva-Martínez, Christopher T. Rodenbeck
2017 J jnl
Multitone ACLR and Its Applications to Linear PA Design.
IEEE Trans. Circuits Syst. II Express Briefs
Haoyu Qian, José Silva-Martínez
2016 J jnl
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS.
IEEE J. Solid State Circuits
Haoyu Qian, Qiyuan Liu, José Silva-Martínez, Sebastian Hoyos
2016 J jnl
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer.
IEEE J. Solid State Circuits
Carlos Briseno-Vidrios, Alexander Edward, Negar Rashidi, José Silva-Martínez
2016 — conf
A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration.
SoCC
Dadian Zhou, Claudio Talarico, José Silva-Martínez
2015 C conf
A 0.6ps jitter 2-16 GHz 130nm CMOS frequency synthesizer for broadband applications.
ISCAS
Yung-Chung Lo, Negar Rashidi, Yin-Huan Hwang, José Silva-Martínez
2015 — conf
A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique.
VLSIC
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
2015 J jnl
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain.
IEEE Trans. Very Large Scale Integr. Syst.
Hyung-Joon Jeon, José Silva-Martínez, Sebastian Hoyos
2015 J jnl
Design Techniques to Improve Blocker Tolerance of Continuous-Time ΔΣ ADCs.
IEEE Trans. Very Large Scale Integr. Syst.
Hemasundar Mohan Geddada, Chang-Joon Park, Hyung-Joon Jeon, José Silva-Martínez, Aydin Ilker Karsilayan, Douglas Garrity
2015 J jnl
Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Very Large Scale Integr. Syst.
Chang-Joon Park, Marvin Onabajo, Hemasundar Mohan Geddada, Aydin Ilker Karsilayan, José Silva-Martínez
2014 — conf
A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOS.
A-SSCC
Haoyu Qian, José Silva-Martínez
2014 — conf
Blocker tolerant wideband continuous time sigma-delta modulator for wireless applications.
MWSCAS
Hemasundar Mohan Geddada, Chang-Joon Park, José Silva-Martínez, Aydin Ilker Karsilayan
2014 — conf
Design of minimally-invasive all-pole analog lowpass filters.
MWSCAS
Saiteja Damera, Aydin Ilker Karsilayan, José Silva-Martínez
2014 — conf
Design techniques for external capacitor-less LDOs with high PSR over wide frequency range.
MWSCAS
Chang-Joon Park, José Silva-Martínez, Marvin Onabajo
2014 J jnl
External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4-4 MHz Range.
IEEE J. Solid State Circuits
Chang-Joon Park, Marvin Onabajo, José Silva-Martínez
2014 J jnl
General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs
Alexander Edward, José Silva-Martínez
2014 — conf
Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes.
MWSCAS
Josep Altet, Eduardo Aldrete-Vidrio, Ferran Reverter, Didac Gómez, José Luis González, Marvin Onabajo, José Silva-Martínez, B. Martineau, X. Perpiñà, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Xavier Aragonès, Xavier Jordà, Miquel Vellvehí, Stefan Dilhaire, Salvador Mir, Diego Mateo
2014 — conf
Welcome to MWSCAS 2014.
MWSCAS
José Silva-Martínez, Edgar Sánchez-Sinencio, José G. Delgado-Frias, Randall L. Geiger
2013 J jnl
A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings.
IEEE Trans. Biomed. Circuits Syst.
Carlos Zamarreño-Ramos, Raghavendra Kulkarni, José Silva-Martínez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
2013 J jnl
A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy.
IEEE J. Solid State Circuits
Hyung-Joon Jeon, Raghavendra Kulkarni, Yung-Chung Lo, Jusung Kim, José Silva-Martínez
2013 C conf
A current-mode flash ADC for low-power continuous-time sigma delta modulators.
ISCAS
Chang-Joon Park, Hemasundar Mohan Geddada, Aydin I. Karsilayan, José Silva-Martínez, Marvin Onabajo
2013 — conf
An external capacitor-less low drop-out regulator with superior PSR and fast transient response.
MWSCAS
Saikrishna Ganta, Chang-Joon Park, Daniel Gitzel, Rafael Rivera, José Silva-Martínez
2013 J jnl
Dual-Level Adaptive Supply Voltage System for Variation Resilience.
IEEE Trans. Very Large Scale Integr. Syst.
Kyu-Nam Shim, Jiang Hu, José Silva-Martínez
2013 — conf
Efficient calibration scheme for high-resolution pipelined ADCs.
MWSCAS
Andreas Larsson, José Silva-Martínez
2013 — conf
Envelope tracking technique with bang-bang slew-rate enhancer for linear wideband RF PAs.
MWSCAS
Richard Turkson, Suraj Prakash, José Silva-Martínez, Herminio Martínez-Garcia
2013 J jnl
Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications.
IEEE J. Solid State Circuits
Jusung Kim, José Silva-Martínez
2013 — conf
Robust compensation scheme for low power capacitor-less low dropout voltage regulator.
MWSCAS
Daniel Gitzel, Rafael Rivera, José Silva-Martínez
2012 J jnl
A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer.
IEEE J. Solid State Circuits
Ahmed A. Helmy, Hyung-Joon Jeon, Yung-Chung Lo, Andreas J. Larsson, Raghavendra Kulkarni, Jusung Kim, José Silva-Martínez, Kamran Entesari
2012 J jnl
A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Xi Chen, Ehab Ahmed Sobhy, Zhuizhuan Yu, Sebastian Hoyos, José Silva-Martínez, Samuel Palermo, Brian M. Sadler
2012 J jnl
An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Haitao Tong, Shanfeng Cheng, Yung-Chung Lo, Aydin I. Karsilayan, José Silva-Martínez
2012 — conf
Blocker and jitter tolerant wideband ΣΔ modulators.
MWSCAS
José Silva-Martínez, Aydin Ilker Karsilayan, Hemasundar Mohan Geddada
2012 — conf
Low-power 3
MWSCAS
Kunmo Kim, José Silva-Martínez
2012 J jnl
UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations.
IEEE Trans. Very Large Scale Integr. Syst.
Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, Jianhong Xiao, José Silva-Martínez
2011 J jnl
A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator.
IEEE J. Solid State Circuits
Mohamed M. Elsayed, Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio
2011 J jnl
A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element.
IEEE J. Solid State Circuits
Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz
2011 J jnl
A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler, José Silva-Martínez
2011 J jnl
Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sebastian Hoyos, Srikanth Pentakota, Zhuizhuan Yu, Ehab Sobhy Abdel Ghany, Xi Chen, Ramy Saad, Samuel Palermo, José Silva-Martínez
2011 J jnl
Corrections to "A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing".
IEEE Trans. Circuits Syst. I Regul. Pap.
Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler, José Silva-Martínez
2011 J jnl
Electrothermal Design Procedure to Observe RF Circuit Power and Linearity Characteristics With a Homodyne Differential Temperature Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap.
Marvin Onabajo, Josep Altet, Eduardo Aldrete-Vidrio, Diego Mateo, José Silva-Martínez
2011 — conf
Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS.
ESSCIRC
Hemasundar Mohan Geddada, José Silva-Martínez, Stewart S. Taylor
2011 J jnl
Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations.
J. Electron. Test.
Marvin Onabajo, Didac Gómez, Eduardo Aldrete-Vidrio, Josep Altet, Diego Mateo, José Silva-Martínez
2011 C conf
Voltage mode driver for low power transmission of high speed serial AER Links.
ISCAS
Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Raghavendra Kulkarni, José Silva-Martínez
2010 J jnl
A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback.
IEEE J. Solid State Circuits
Cho-Ying Lu, Marvin Onabajo, Venkata Gadde, Yung-Chung Lo, Hsien-Pu Chen, Vijayaramalingam Periasamy, José Silva-Martínez
2010 J jnl
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth.
IEEE J. Solid State Circuits
Cho-Ying Lu, Jose Fabian Silva-Rivas, Praveena Kode, José Silva-Martínez, Sebastian Hoyos
2010 C conf
A broadband 470-862 MHz direct conversion CMOS receiver.
ISCAS
Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, José Silva-Martínez, Jianhong Xiao
2010 — conf
A dual-level adaptive supply voltage system for variation resilience.
ISQED
Kyu-Nam Shim, Jiang Hu, José Silva-Martínez
2010 J jnl
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications.
IEEE J. Solid State Circuits
Mohamed Mobarak, Marvin Onabajo, José Silva-Martínez, Edgar Sánchez-Sinencio
2009 — conf
A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider.
CICC
Yung-Chung Lo, Hsien-Pu Chen, José Silva-Martínez, Sebastian Hoyos
2009 — conf
A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element.
ISSCC
Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz
2009 J jnl
A Graphical Approach to Teaching Amplifier Design at the Undergraduate Level.
IEEE Trans. Educ.
Rida S. Assaad, José Silva-Martínez
2009 J jnl
An On-Chip Loopback Block for RF Transceiver Built-In Test.
IEEE Trans. Circuits Syst. II Express Briefs
Marvin Onabajo, José Silva-Martínez, Félix O. Fernandez-Rodriguez, Edgar Sánchez-Sinencio
2009 J jnl
Design of Three-Stage Class-AB 16ΩHeadphone Driver Capable of Handling Wide Range of Load Capacitance.
IEEE J. Solid State Circuits
Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
2009 A conf
Non-invasive RF built-in testing using on-chip temperature sensors.
ITC
Eduardo Aldrete-Vidrio, Marvin Onabajo, Josep Altet, Diego Mateo, José Silva-Martínez
2009 J jnl
Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers.
VLSI Design
Rida S. Assaad, José Silva-Martínez
2009 J jnl
System and Circuit Design for an MB-OFDM UWB Frequency Synthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chinmaya Mishra, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio, José Silva-Martínez
2009 J jnl
The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier.
IEEE J. Solid State Circuits
Rida S. Assaad, José Silva-Martínez
2008 — conf
A 1.2mW 1.6Vpp-Swing Class-AB 16Ω Headphone Driver Capable of Handling Load Capacitance up to 22nF.
ISSCC
Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
2008 J jnl
A Broadband CMOS Amplitude Detector for On-Chip RF Measurements.
IEEE Trans. Instrum. Meas.
Alberto Valdes-Garcia, Radhika Venkatasubramanian, José Silva-Martínez, Edgar Sánchez-Sinencio
2008 J jnl
A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer.
IEEE J. Solid State Circuits
David Hernandez-Garduno, José Silva-Martínez
2008 J jnl
A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaohua Fan, Marvin Onabajo, Félix O. Fernandez-Rodriguez, José Silva-Martínez, Edgar Sánchez-Sinencio
2008 J jnl
A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jinghua Li, José Silva-Martínez, Brian Brunn, Shahriar Rokhsaz, Moises E. Robinson
2008 — conf
A low power 1.3GHz dual-path current mode Gm-C filter.
CICC
Manisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
2008 J jnl
Applications of Multipath Transform-Domain Charge-Sampling Wide-Band Receivers.
IEEE Trans. Circuits Syst. II Express Briefs
Pradeep Kotte Prakasam, Mandar Kulkarni, Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 J jnl
A 1.1 GHz Fifth Order Active-LC Butterworth Type Equalizing Filter.
IEEE J. Solid State Circuits
Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 J jnl
A 30-MHz Fifth-Order Elliptic Low-Pass CMOS Filter With 65-dB Spurious-Free Dynamic Range.
IEEE Trans. Circuits Syst. I Regul. Pap.
Artur J. Lewinski, José Silva-Martínez
2007 J jnl
A 63 dB SNR, 75-mW Bandpass RF ΣΔ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-µm SiGe BiCMOS Technology.
IEEE J. Solid State Circuits
Bharath Kumar Thandri, José Silva-Martínez
2007 — conf
A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay Cells.
ISSCC
David Hernandez-Garduno, José Silva-Martínez
2007 J jnl
A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz.
IEEE J. Solid State Circuits
Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin Ilker Karsilayan
2007 J jnl
A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner.
IEEE J. Solid State Circuits
Jianhong Xiao, Iuri Mehr, José Silva-Martínez
2007 J jnl
An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication.
IEEE J. Solid State Circuits
Alberto Valdes-Garcia, Chinmaya Mishra, Faramarz Bahmani, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 J jnl
An Injection-Locked Frequency Divider With Multiple Highly Nonlinear Injection Stages and Large Division Ratios.
IEEE Trans. Circuits Syst. II Express Briefs
Haitao Tong, Shanfeng Cheng, Aydin I. Karsilayan, José Silva-Martínez
2007 J jnl
Estimation of Aliasing Effects Due to Periodical Nonuniform Individual Sampling in High-
IEEE Trans. Circuits Syst. II Express Briefs
David Hernandez-Garduno, José Silva-Martínez, José L. Ausín
2007 J jnl
Full On-Chip CMOS Low-Dropout Voltage Regulator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Robert Jon Milliken, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 J jnl
Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band G
IEEE Trans. Circuits Syst. I Regul. Pap.
Manisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 J jnl
Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting.
VLSI Design
Jianhong Xiao, Guang Zhang, Tianwei Li, José Silva-Martínez
2007 J jnl
Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector.
IEEE Trans. Circuits Syst. II Express Briefs
Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin I. Karsilayan
2006 J jnl
A 10.7-MHz sixth-order SC ladder filter in 0.35-μm CMOS technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jozef Adut, José Silva-Martínez, Miguel Rocha-Pérez
2006 J jnl
A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-μm CMOS technology.
IEEE Trans. Circuits Syst. II Express Briefs
Bharath Kumar Thandri, José Silva-Martínez
2006 J jnl
A CMOS 140-mW fourth-order continuous-time low-pass filter stabilized with a class AB common-mode feedback operating at 550 MHz.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pankaj Pandey, José Silva-Martínez, Xuemei Liu
2006 J jnl
A High-Frequency Transconductor Using a Robust Nonlinearity Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs
Artur J. Lewinski, José Silva-Martínez
2006 J jnl
An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing.
IEEE J. Solid State Circuits
Alberto Valdes-Garcia, Faisal Abdel-Latif Hussien, José Silva-Martínez, Edgar Sánchez-Sinencio
2006 J jnl
An overview of feed-forward design techniques for high-gain wideband operational transconductance amplifiers.
Microelectron. J.
Bharath Kumar Thandri, José Silva-Martínez
2006 J jnl
Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching.
IEEE Trans. Circuits Syst. II Express Briefs
Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin I. Karsilayan
2006 J jnl
Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jianlong Chen, Edgar Sánchez-Sinencio, José Silva-Martínez
2006 J jnl
On-Chip Testing Techniques for RF Wireless Transceivers.
IEEE Des. Test Comput.
Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
2006 J jnl
Quasi Rail-to-Rail Very Low-Voltage OPAMP With a Single pMOS Input Differential Pair.
IEEE Trans. Circuits Syst. II Express Briefs
David Báez-Villegas, José Silva-Martínez
2005 Misc conf
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers.
VTS
Alberto Valdes-Garcia, Radhika Venkatasubramanian, Rangakrishnan Srinivasan, José Silva-Martínez, Edgar Sánchez-Sinencio
2005 J jnl
An On-Chip Spectrum Analyzer for Analog Built-In Testing.
J. Electron. Test.
Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
2004 — conf
6.8 mW 2.5 Gb/s and 42.5 mW 5 Gb/s 1: 8 CMOS demultiplexers.
ISCAS (4)
Shanfeng Cheng, José Silva-Martínez
2004 — conf
A 500 MHz OTA-C 4
CICC
Pankaj Pandey, José Silva-Martínez, Xuemei Liu
2004 J jnl
A frequency compensation scheme for LDO voltage regulators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chaitanya K. Chava, José Silva-Martínez
2004 Misc conf
An On-Chip Transfer Function Characterization System for Analog Built-in Testing.
VTS
Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
2004 — conf
Bandwidth enhancement of multi-stage amplifiers using active feedback.
ISCAS (1)
M. Reza Samadi, Aydin I. Karsilayan, José Silva-Martínez
2004 J jnl
OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB.
IEEE Trans. Circuits Syst. II Express Briefs
Artur J. Lewinski, José Silva-Martínez
2003 J jnl
A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-μm CMOS.
IEEE J. Solid State Circuits
Fikret Dulger, Edgar Sánchez-Sinencio, José Silva-Martínez
2003 J jnl
A 2-V
IEEE J. Solid State Circuits
Mingdeng Chen, José Silva-Martínez, Shahriar Rokhsaz, Moises E. Robinson
2003 J jnl
A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier.
IEEE J. Solid State Circuits
Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez, Sherif H. K. Embabi
2003 J jnl
A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators.
IEEE J. Solid State Circuits
Ahmed N. Mohieldin, Edgar Sánchez-Sinencio, José Silva-Martínez
2003 — conf
A 58dB SNR 6
CICC
José Silva-Martínez, Joseph Adut, Miguel Rocha-Pérez
2003 J jnl
A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system.
IEEE J. Solid State Circuits
José Silva-Martínez, Joseph Adut, José Miguel Rocha-Pérez, Moises E. Robinson, Shahriar Rokhsaz
2003 — conf
A 92MHz, 80dB peak SNR SC bandpass ΣΔ modulator based on a high GBW OTA with no Miller capacitors in 0.35μm CMOS technology.
CICC
Bharath Kumar Thandri, José Silva-Martínez, José Miguel Rocha-Pérez, Jing Wang
2003 J jnl
A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector.
IEEE J. Solid State Circuits
Ahmed Nader Mohieldin, Edgar Sánchez-Sinencio, José Silva-Martínez
2003 J jnl
A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors.
IEEE J. Solid State Circuits
Bharath Kumar Thandri, José Silva-Martínez
2003 — conf
An Analog Integrated Circuit Design Laboratory.
MSE
Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio
2003 — conf
Cascode transconductance amplifiers for HF switched-capacitor applications.
ISCAS (1)
Jozef Adut, José Silva-Martínez
2003 J jnl
Compact sub-hertz OTA-C filter design with interface-trap charge pump.
IEEE J. Solid State Circuits
Adriana Becker-Gomez, Ugur Çilingiroglu, José Silva-Martínez
2003 J jnl
Nonlinear effects in pseudo differential OTAs with CMFB.
IEEE Trans. Circuits Syst. II Express Briefs
A. N. Mohieldin, Edgar Sánchez-Sinencio, José Silva-Martínez
2003 — conf
OTA linearity enhancement technique for high frequency applications with IM3 below -65dB.
CICC
Artur J. Lewinski, José Silva-Martínez
2002 — conf
A 1.8V CMOS, 80-200MHz continuous-time 4th order 0.05° equiripple linear phase filter with automatic tuning system.
ISCAS (5)
Mingdeng Chen, José Silva-Martínez, Shahriar Rokhsaz, Moises E. Robinson
2002 — conf
A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling.
ISCAS (4)
Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez
2002 J jnl
A CMOS transconductance amplifier architecture with wide tuning range for very low frequency applications.
IEEE J. Solid State Circuits
Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez
2002 — conf
A high-Q, switched-capacitor filter with reduced capacitance spread using a randomized nonuniform sampling technique.
ISCAS (4)
Jozef Adut, José Silva-Martínez
2002 — conf
A robust frequency compensation scheme for LDO regulators.
ISCAS (5)
Chaitanya K. Chava, José Silva-Martínez
2002 — conf
On-chip spectrum analyzer for built-in testing analog ICs.
ISCAS (5)
Marcia G. Méndez-Rivera, José Silva-Martínez, Edgar Sánchez-Sinencio
2002 J jnl
Transconductance amplifier structures with very small transconductances: a comparative design approach.
IEEE J. Solid State Circuits
Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez
2001 — conf
A 150 MHz continuous-time seventh order 0.05° equiripple linear phase filter with automatic tuning system.
ISCAS (1)
Adan Lopez-Martinez, Regina Antonio-Chavez, José Silva-Martínez
2001 — conf
A feedforward compensation scheme for high gain wideband amplifiers.
ICECS
Bharath Kumar Thandri, José Silva-Martínez, Franco Maloberti
2001 — conf
A low voltage operational transconductance amplifier using common mode feedforward for high frequency switched capacitor circuits.
ISCAS (1)
Asit Shankar, José Silva-Martínez, Edgar Sánchez-Sinencio
2001 — conf
Linear cellular neural networks.
ISCAS (3)
Federico Lobato-Lopez, José Silva-Martínez, Edgar Sánchez-Sinencio
2000 C conf
A fully-programmable temperature-compensated analogue circuit for Gaussian functions.
ISCAS
Miguel Melendez-Rodriguez, José Silva-Martínez
2000 C conf
Different operational transconductance amplifier topologies for obtaining very small transconductances.
ISCAS
Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez
1999 — conf
Design considerations for high performance very low frequency filters.
ISCAS (2)
José Silva-Martínez, S. Solis-Bustos
1999 — conf
Transimpedance amplifiers for optical fiber systems based on common-base transistors.
ISCAS (6)
J. Martínez-Castillo, José Silva-Martínez
1998 — conf
A 4 Hz low-pass continuous-time filter.
ICECS
Sergio A. Solis-Bustos, José Silva-Martínez
1998 — conf
Efficient clock recovery architecture.
ICECS
Marcia G. Méndez-Rivera, Ari Yakov Valero-López, José Silva-Martínez, Edgar Sánchez-Sinencio
1995 C conf
A CMOS Preamplifier for Electret Microphones.
ISCAS
José Silva-Martínez, Jorge Salcedo-Suñer
1994 C conf
A Programmable Switched-Capacitor Filter.
ISCAS
José Silva-Martínez
1994 C conf
Effect of the Transistor Mismatches on the Performance of Fully-Differential OTAS.
ISCAS
José Silva-Martínez
1993 — book
High-performance CMOS continuous-time filters.
José Silva-Martínez, Michiel Steyaert, Willy M. C. Sansen