José Pineda de Gyvez

126 papers A* 2A 24B 3C 12Misc 5Journal 45Unranked 34

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An Ultra-Low-Leakage Microcontroller With Configurable Power Management for Energy Harvesting IoT Devices. IEEE Access Shima Sedighiani, Bram Van Bolderik, Barry de Bruin, Kamlesh Singh, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
2023	J	`jnl`	A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods. IEEE Trans. Circuits Syst. II Express Briefs Shima Sedighiani, Kamlesh Singh, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
2021	—	`conf`	A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT. ISQED Shima Sedighiani, Kamlesh Singh, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
2021	J	`jnl`	Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation. IEEE Trans. Very Large Scale Integr. Syst. Kamlesh Singh, Barry de Bruin, Hailong Jiao, Jos Huisken, Henk Corporaal, José Pineda de Gyvez
2021	J	`jnl`	Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection. IEEE Trans. Biomed. Circuits Syst. Barry de Bruin, Kamlesh Singh, Ying Wang, Jos Huisken, José Pineda de Gyvez, Henk Corporaal
2021	J	`jnl`	Twenty Years of Near/Sub-Threshold Design Trends and Enablement. IEEE Trans. Circuits Syst. II Express Briefs Kamlesh Singh, José Pineda de Gyvez
2020	—	`conf`	An Electromagnetic Energy Harvester and Power Management in 28-nm FDSOI for IoT. MECO Shima Sedighiani, Kamlesh Singh, Jos Huisken, Roel Jordans, Pieter Harpe, José Pineda de Gyvez
2020	J	`jnl`	Heuristic Methods for Fine-Grain Exploitation of FDSOI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez
2020	A	`conf`	Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN. DATE Emad A. Ibrahim, Marc Geilen, Jos Huisken, Min Li, José Pineda de Gyvez
2020	J	`jnl`	Multi-Angle Fusion for Low-Cost Near-Field Ultrasonic in-Air Gesture Recognition. IEEE Access Emad A. Ibrahim, Marc Geilen, Min Li, José Pineda de Gyvez
2020	—	`conf`	Optimal bounded-skew steiner trees to minimize maximum SLIP Hamed Fatemi, Andrew B. Kahng, Minsoo Kim, José Pineda de Gyvez
2020	A	`conf`	Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator. DATE Paul Detterer, Cumhur Erdin, Jos Huisken, Hailong Jiao, Majid Nabi, Twan Basten, José Pineda de Gyvez
2019	A	`conf`	Chip Health Tracking Using Dynamic In-Situ Delay Monitoring. DATE Hadi Ahmadi Balef, Kees Goossens, José Pineda de Gyvez
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	J	`jnl`	Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs. Integr. P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini
2019	J	`jnl`	Enhancing sensitivity-based power reduction for an industry IC design context. Integr. Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez
2019	C	`conf`	Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network. DSD Emad A. Ibrahim, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
2019	—	`conf`	PRESS/HOLD/RELEASE Ultrasonic Gestures and Low Complexity Recognition Based on TCN. SiPS Emad A. Ibrahim, Min Li, José Pineda de Gyvez
2019	J	`jnl`	Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention. IEEE Trans. Very Large Scale Integr. Syst. Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez
2019	A	`conf`	Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver. DATE Paul Detterer, Cumhur Erdin, Majid Nabi, José Pineda de Gyvez, Twan Basten, Hailong Jiao
2019	—	`conf`	Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. SoCC Kamlesh Singh, Barry de Bruin, Jos Huisken, Hailong Jiao, José Pineda de Gyvez
2018	J	`jnl`	CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units. IEEE Trans. Computers Xun Jiao, Abbas Rahimi, Yu Jiang, Jianguo Wang, Hamed Fatemi, José Pineda de Gyvez, Rajesh K. Gupta
2018	—	`conf`	Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths. ACM Great Lakes Symposium on VLSI Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez
2018	—	`conf`	Low power latch based design with smart retiming. ISQED Kamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez
2018	C	`conf`	Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. ISCAS Kamlesh Singh, Omar Alejandro Rodriguez Rosas, Hailong Jiao, Jos Huisken, José Pineda de Gyvez
2018	—	`conf`	Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs. PATMOS P. Anagnostou, Andres Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini
2017	J	`jnl`	A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling. IEEE J. Solid State Circuits Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, Kofi A. A. Makinwa, José Pineda de Gyvez
2017	A	`conf`	A scan-chain based state retention methodology for IoT processors operating on intermittent energy. DATE Pascal Alexander Hager, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
2017	—	`conf`	An analytical model for interdependent setup/hold-time characterization of flip-flops. ISQED Hadi Ahmadi Balef, Hailong Jiao, José Pineda de Gyvez, Kees Goossens
2017	—	`conf`	Floorplan and placement methodology for improved energy reduction in stacked power-domain design. ASP-DAC Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez
2017	J	`jnl`	Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors. Microprocess. Microsystems Andres Gomez, Andrea Bartolini, Davide Rossi, Baris Can Kara, Hamed Fatemi, José Pineda de Gyvez, Luca Benini
2017	J	`jnl`	Logic Design Partitioning for Stacked Power Domains. IEEE Trans. Very Large Scale Integr. Syst. Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez
2017	—	`conf`	Reconfigurable Support Vector Machine Classifier with Approximate Computing. ISVLSI Martin Van Leussen, Jos Huisken, Lei Wang, Hailong Jiao, José Pineda de Gyvez
2016	—	`conf`	A microcontroller with 96% power-conversion efficiency using stacked voltage domains. VLSI Circuits Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, José Pineda de Gyvez, Kofi A. A. Makinwa
2016	A	`conf`	Circuit valorization in the IC design ecosystem. ICCAD José Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt
2016	A*	`conf`	Lower power by voltage stacking: a fine-grained system design approach. DAC Kristof Blutman, Ajay Kapoor, Jacinto Garcia Martinez, Hamed Fatemi, José Pineda de Gyvez
2015	J	`jnl`	A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers. Microprocess. Microsystems Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez
2015	J	`jnl`	An Improved Methodology for Resilient Design Implementation. ACM Trans. Design Autom. Electr. Syst. Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez
2015	A	`conf`	Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. DATE Andres Gomez, Christian Pinto, Andrea Bartolini, Davide Rossi, Luca Benini, Hamed Fatemi, José Pineda de Gyvez
2015	C	`conf`	Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing. VLSI-SoC Mini Jayakrishnan, Alan Chang, José Pineda de Gyvez, Tae-Hyoung Kim
2015	—	`conf`	Supervised learning based model for predicting variability-induced timing errors. NEWCAS Xun Jiao, Abbas Rahimi, Balakrishnan Narayanaswamy, Hamed Fatemi, José Pineda de Gyvez, Rajesh K. Gupta
2014	J	`jnl`	Digital Systems Power Management for High Performance Mixed Signal Platforms. IEEE Trans. Circuits Syst. I Regul. Pap. Ajay Kapoor, Cas Groot, Gerard Villar Pique, Hamed Fatemi, Juan Diego Echeverri, Leo Sevat, Maarten Vertregt, Maurice Meijer, Vibhu Sharma, Yu Pu, José Pineda de Gyvez
2014	A	`conf`	Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling. DATE Yu Pu, Juan Diego Echeverri, Maurice Meijer, José Pineda de Gyvez
2014	A	`conf`	Standard cell library tuning for variability tolerant designs. DATE Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez
2014	—	`conf`	Sub-threshold custom standard cell library validation. ISQED Bo Liu, Maryam Ashouei, Tobias Gemmeke, José Pineda de Gyvez
2013	—	`conf`	A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers. NORCHIP Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez
2013	J	`jnl`	Architectural Analysis for Wirelessly Powered Computing Platforms. IEEE Trans. Very Large Scale Integr. Syst. Ajay Kapoor, José Pineda de Gyvez
2013	J	`jnl`	Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking. IEEE Trans. Computers Hamid Reza Pourshaghaghi, José Pineda de Gyvez
2012	—	`conf`	A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation. SoCC Sebastian M. Londono, José Pineda de Gyvez
2012	J	`jnl`	Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. Maurice Meijer, José Pineda de Gyvez
2012	J	`jnl`	Digital Adaptive Calibration of Multi-Step Analog to Digital Converters. J. Low Power Electron. Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez
2012	J	`jnl`	Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS. IEEE Trans. Instrum. Meas. Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez
2012	A	`conf`	Sliding-Mode Control to Compensate PVT Variations in dual core systems. DATE Hamid Reza Pourshaghaghi, Hamed Fatemi, José Pineda de Gyvez
2012	A*	`conf`	Standard cell sizing for subthreshold operation. DAC Bo Liu, Maryam Ashouei, Jos Huisken, José Pineda de Gyvez
2011	A	`conf`	A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs. ISLPED Amir Zjajo, José Pineda de Gyvez
2011	C	`conf`	Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage. DSD Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez
2011	J	`jnl`	Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs. IEEE Trans. Circuits Syst. I Regul. Pap. Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico, Nick van der Meijs
2010	C	`conf`	A forward body bias generator for digital CMOS circuits with supply voltage scaling. ISCAS Maurice Meijer, José Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, Maarten Vertregt
2010	—	`conf`	Body bias driven design synthesis for optimum performance per area. ISQED Maurice Meijer, José Pineda de Gyvez
2010	—	`conf`	Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. ICECS Hamid Reza Pourshaghaghi, José Pineda de Gyvez
2010	J	`jnl`	Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation. J. Low Power Electron. Maurice Meijer, José Pineda de Gyvez, Ajay Kapoor
2009	—	`conf`	An energy-aware multiplier based on a Configurable-Reuse of points design methodology. ICECS Sebastian M. Londono, José Pineda de Gyvez
2009	J	`jnl`	Analog Automatic Test Pattern Generation for Quasi-Static Structural Test. IEEE Trans. Very Large Scale Integr. Syst. Amir Zjajo, José Pineda de Gyvez
2009	—	`conf`	Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller. ICECS Hamid Reza Pourshaghaghi, José Pineda de Gyvez
2008	—	`conf`	Calibration and Debugging of Multi-step Analog to Digital Converters. DELTA Amir Zjajo, José Pineda de Gyvez
2008	A	`conf`	Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. DATE Amir Zjajo, José Pineda de Gyvez
2008	C	`conf`	Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. DDECS Amir Zjajo, Shaji Krishnan, José Pineda de Gyvez
2007	J	`jnl`	Efficient testing and diagnosis of faulty power switches in SOCs. IET Comput. Digit. Tech. Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
2007	A	`conf`	Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. DATE Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez
2006	J	`jnl`	An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. J. Low Power Electron. Josep Rius, Maurice Meijer, José Pineda de Gyvez
2006	J	`jnl`	Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. J. Electron. Test. Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud
2006	B	`conf`	Testing and Diagnosis of Power Switches in SOCs. ETS Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
2006	J	`jnl`	Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique. IEEE J. Solid State Circuits Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
2005	J	`jnl`	A capacitor cross-coupled common-gate low-noise amplifier. IEEE Trans. Circuits Syst. II Express Briefs Wei Zhuo, Xiaoyong Li, Sudip Shekhar, Sherif H. K. Embabi, José Pineda de Gyvez, David J. Allstot, Edgar Sánchez-Sinencio
2005	—	`conf`	An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. PATMOS Josep Rius, José Pineda de Gyvez, Maurice Meijer
2005	B	`conf`	Evaluation of signature-based testing of RF/analog circuits. ETS Amir Zjajo, José Pineda de Gyvez
2005	A	`conf`	Functional vs. multi-VDD testing of RF circuits. ITC Estella Silva, José Pineda de Gyvez, Guido Gronthoud
2005	—	`conf`	Glitch-free discretely programmable clock generation on chip. ISCAS (2) Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
2005	—	`conf`	Limits to performance spread tuning using adaptive voltage and body biasing. ISCAS (1) Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
2005	J	`jnl`	Multi-VDD Testing for Analog Circuits. J. Electron. Test. José Pineda de Gyvez, Guido Gronthoud, Rashid Amine
2005	A	`conf`	On-chip digital power supply control for system-on-chip applications. ISLPED Maurice Meijer, José Pineda de Gyvez, Ralph Otten
2005	A	`conf`	Power-scan chain: design for analog testability. ITC Amir Zjajo, Henk Jan Bergveld, Rodger Schuttert, José Pineda de Gyvez
2005	—	`conf`	Programmable techniques for cell stability test and debug in embedded SRAMs. CICC Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez, Mohamed Azimane
2005	A	`conf`	Word line pulsing technique for stability fault detection in SRAM cells. ITC Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev
2004	A	`conf`	AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. ITC Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
2004	Misc	`conf`	Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. VTS Josep Rius Vázquez, José Pineda de Gyvez
2004	J	`jnl`	Built-in current sensor for ΔI IEEE J. Solid State Circuits Josep Rius Vázquez, José Pineda de Gyvez
2004	Misc	`conf`	Low Energy Switch Block For FPGAs. VLSI Design Rohini Krishnan, José Pineda de Gyvez
2004	A	`conf`	Low energy FPGA interconnect design. FPGA Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
2004	—	`conf`	Low energy FPGA interconnect design. ACM Great Lakes Symposium on VLSI Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
2004	A	`conf`	Power Supply Noise Monitor for Signal Integrity Faults. DATE Josep Rius Vázquez, José Pineda de Gyvez
2004	A	`conf`	Power Supply Ramping for Quasi-static Testing of PLLs. ITC José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller
2004	A	`conf`	Technology exploration for adaptive power and frequency scaling in 90nm CMOS. ISLPED Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez
2004	J	`jnl`	Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits. IEEE J. Solid State Circuits José Pineda de Gyvez, Hans Tuinhout
2003	—	`conf`	An Analog Integrated Circuit Design Laboratory. MSE Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio
2003	B	`conf`	Encoded-Low Swing Technique for Ultra Low Power Interconnect. FPL Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick
2003	J	`jnl`	Prelayout interconnect yield prediction. IEEE Trans. Very Large Scale Integr. Syst. Phillip Christie, José Pineda de Gyvez
2003	—	`conf`	Process-variability aware delay fault testing of ΔV ETW Daniel Arumí-Delgado, Rosa Rodríguez-Montañés, José Pineda de Gyvez, Guido Gronthoud
2003	Misc	`conf`	Threshold Voltage Mismatch (DeltaVT) Fault Modeling. VTS José Pineda de Gyvez, Rosa Rodríguez-Montañés
2003	A	`conf`	VDD Ramp Testing for RF Circuits. ITC José Pineda de Gyvez, Guido Gronthoud, Rashid Amine
2002	J	`jnl`	Resistance Characterization for Weak Open Defects. IEEE Des. Test Comput. Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez
2001	Misc	`conf`	Average Leakage Current Estimation of CMOS Logic Circuits. VTS José Pineda de Gyvez, Eric van de Wetering
2001	—	`conf`	Pre-layout prediction of interconnect manufacturability. SLIP Phillip Christie, José Pineda de Gyvez
2001	—	`conf`	Yield modeling and BEOL fundamentals. SLIP José Pineda de Gyvez
2000	J	`jnl`	Full-signature real-time corrosion detection of underground casing pipes. IEEE Trans. Instrum. Meas. Jiming Yin, Mi Lu, José Pineda de Gyvez
2000	J	`jnl`	Nonlinear Computability Based on Chaos. Int. J. Bifurc. Chaos Gabriele Manganaro, José Pineda de Gyvez
2000	J	`jnl`	Real-time wavelet-integrated corrosion detection system for casing pipes. Integr. Comput. Aided Eng. Jiming Yin, José Pineda de Gyvez, Mi Lu
2000	—	`conf`	Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. DFT Madhuban Kishor, José Pineda de Gyvez
1999	—	`conf`	CMOS cryptosystem using a Lorenz chaotic oscillator. ISCAS (5) Octavio A. González, Gunhee Han, José Pineda de Gyvez, Edgar Sánchez-Sinencio
1999	—	`conf`	Chaotic generation of PN sequences: a VLSI implementation. ISCAS (5) A. Dornbusch, José Pineda de Gyvez
1999	J	`jnl`	Subband coding and image compression using CNN. Int. J. Circuit Theory Appl. Oscar Moreira-Tamayo, José Pineda de Gyvez
1998	J	`jnl`	Time multiplexed color image processing based on a CNN with cell-state outputs. IEEE Trans. Very Large Scale Integr. Syst. Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio
1997	C	`conf`	DNA computing based on chaos. ICEC Gabriele Manganaro, José Pineda de Gyvez
1996	J	`jnl`	Color image processing in a cellular neural-network environment. IEEE Trans. Neural Networks Chi-Chien Lee, José Pineda de Gyvez
1996	—	`conf`	Preprocessing operators for image compression using cellular neural networks. ICNN Oscar Moreira-Tamayo, José Pineda de Gyvez
1996	J	`jnl`	Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing. Real Time Imaging Apollo Q. Fong, Ajay Kanji, José Pineda de Gyvez
1995	C	`conf`	A Universal Interface Between PC and Neural Networks Hardware. ISCAS Apollo Q. Fong, Ajay Kanji, Edgar Sánchez-Sinencio, José Pineda de Gyvez
1995	C	`conf`	Time Domain Analog Wavelet Transform in Real-Time. ISCAS Oscar Moreira-Tamayo, José Pineda de Gyvez
1994	Misc	`conf`	A power supply ramping and current measurement based technique for analog fault diagnosis. VTS Shyam S. Somayajula, Edgar Sánchez-Sinencio, José Pineda de Gyvez
1994	C	`conf`	Behavioral Testing of Cellular Neural Networks. ISCAS John Willis, José Pineda de Gyvez
1994	C	`conf`	Single-Layer CNN Simulator. ISCAS Chi-Chien Lee, José Pineda de Gyvez
1994	C	`conf`	Time-Mulitplexing CNN Simulator. ISCAS Chi-Chien Lee, José Pineda de Gyvez
1993	—	`book`	Integrated circuit defect-sensitivity - theory and computational models. José Pineda de Gyvez
1992	J	`jnl`	IC defect sensitivity for footprint-type spot defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José Pineda de Gyvez, Chennian Di
1989	A	`conf`	A layout defect-sensitivity extractor. ICCAD José Pineda de Gyvez, Jochen A. G. Jess
1989	J	`jnl`	On the design and implementation of a wafer yield editor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José Pineda de Gyvez, Jochen A. G. Jess