José Monteiro

109 papers A* 4A 9B 1C 14Misc 3Journal 38Unranked 36

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Accelerating a restarted Krylov method for matrix functions with randomization. CoRR Nicolas L. Guidotti, Per-Gunnar Martinsson, Juan A. Acebrón, José Monteiro
2025	J	`jnl`	Correction to: A Fast Monte Carlo Algorithm for Evaluating Matrix Functions with Application in Complex Networks. J. Sci. Comput. Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro
2025	J	`jnl`	Survey of a class of iterative row-action methods: The Kaczmarz method. Numer. Algorithms Inês A. Ferreira, Juan A. Acebrón, José Monteiro
2024	J	`jnl`	A Fast Monte Carlo Algorithm for Evaluating Matrix Functions with Application in Complex Networks. J. Sci. Comput. Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro
2024	J	`jnl`	A stochastic method for solving time-fractional differential equations. Comput. Math. Appl. Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro
2024	J	`jnl`	Parallelization Strategies for the Randomized Kaczmarz Algorithm on Large-Scale Dense Systems. CoRR Inês A. Ferreira, Juan A. Acebrón, José Monteiro
2024	J	`jnl`	Survey of a Class of Iterative Row-Action Methods: The Kaczmarz Method. CoRR Inês A. Ferreira, Juan A. Acebrón, José Monteiro
2023	J	`jnl`	A Fast Monte Carlo algorithm for evaluating matrix functions with application in complex networks. CoRR Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro
2023	J	`jnl`	A Stochastic Method for Solving Time-Fractional Differential Equations. CoRR Nicolas L. Guidotti, Juan A. Acebrón, José Monteiro
2023	J	`jnl`	Mobile Localization Techniques for Wireless Sensor Networks: Survey and Recommendations. ACM Trans. Sens. Networks Leonardo L. de Oliveira, Gabriel H. Eisenkraemer, Everton Alceu Carara, João B. Martins, José Monteiro
2022	J	`jnl`	A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. Remote. Sens. Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte
2022	J	`jnl`	A distributed Monte Carlo based linear algebra solver applied to the analysis of large complex networks. Future Gener. Comput. Syst. Filipe Magalhães, José Monteiro, Juan A. Acebrón, José R. Herrero
2022	—	`conf`	OmpSs-2 and OpenACC Interoperation. WACCPD@SC Orestis Korakitis, Simon Garcia De Gonzalo, Nicolas L. Guidotti, João Barreto, José Monteiro, Antonio J. Peña
2021	J	`jnl`	Dynamic Page Placement on Real Persistent Memory Systems. CoRR Miguel Marques, Ilia Kuzmin, João Barreto, José Monteiro, Rodrigo Rodrigues
2021	—	`conf`	Particle-In-Cell Simulation Using Asynchronous Tasking. Euro-Par Nicolas L. Guidotti, Pedro Ceyrat, João Barreto, José Monteiro, Rodrigo Rodrigues, Ricardo Fonseca, Xavier Martorell, Antonio J. Peña
2021	J	`jnl`	Particle-In-Cell Simulation using Asynchronous Tasking. CoRR Nicolas L. Guidotti, Pedro Ceyrat, João Barreto, José Monteiro, Rodrigo Rodrigues, Ricardo Fonseca, Xavier Martorell, Antonio J. Peña
2020	J	`jnl`	A highly parallel algorithm for computing the action of a matrix exponential on a vector based on a multilevel Monte Carlo method. Comput. Math. Appl. Juan A. Acebrón, José R. Herrero, José Monteiro
2020	J	`jnl`	Radix-2 IET Circuits Devices Syst. Ahmed Liacha, Abdelkrim Kamel Oudjida, Mohammed Bakiri, José Monteiro, Paulo F. Flores
2020	—	`conf`	Short-circuit Analysis using a Parallel QBF Solver. DCIS Rafael Santos, João Afonso, José Monteiro
2019	—	`ed.`	VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Michail Maniatakos, Ibrahim Abe M. Elfadel, Matteo Sonza Reorda, H. Fatih Ugurdag, José Monteiro, Ricardo Reis
2018	—	`book`	Computer Architecture - Digital Circuits to Microprocessors Computer Architecture Guilherme Arroz, José Monteiro, Arlindo L. Oliveira
2017	—	`conf`	A variable RADIX-2 NEWCAS Ahmed Liacha, Abdelkrim Kamel Oudjida, Farid Ferguene, José Monteiro, Paulo F. Flores
2017	A	`conf`	Analysis of short-circuit conditions in logic circuits. DATE João Afonso, José Monteiro
2016	J	`jnl`	A novel method for the approximation of multiplierless constant matrix vector multiplication. EURASIP J. Embed. Syst. Levent Aksoy, Paulo F. Flores, José Monteiro
2016	J	`jnl`	Automatic equivalence checking of programs with uninterpreted functions and integer arithmetic. Int. J. Softw. Tools Technol. Transf. Nuno P. Lopes, José Monteiro
2015	C	`conf`	A Novel Method for the Approximation of Multiplierless Constant Matrix Vector Multiplication. EUC Levent Aksoy, Paulo F. Flores, José Monteiro
2015	C	`conf`	Approximation of multiple constant multiplications using minimum look-up tables on FPGA. ISCAS Levent Aksoy, Paulo F. Flores, José Monteiro
2015	J	`jnl`	Exact and Approximate Algorithms for the Filter Design Optimization Problem. IEEE Trans. Signal Process. Levent Aksoy, Paulo F. Flores, José Monteiro
2015	J	`jnl`	Quaternary Logic Lookup Table in Standard CMOS. IEEE Trans. Very Large Scale Integr. Syst. Diogo Brito, Taimur Gibran Rabuske, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
2014	J	`jnl`	A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures. Circuits Syst. Signal Process. Levent Aksoy, Paulo F. Flores, José Monteiro
2014	C	`conf`	ECHO: A novel method for the multiplierless design of constant array vector multiplication. ISCAS Levent Aksoy, Paulo F. Flores, José Monteiro
2014	C	`conf`	Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA. ICCD Levent Aksoy, Paulo F. Flores, José Monteiro
2014	J	`jnl`	Multiplierless Design of Folded DSP Blocks. ACM Trans. Design Autom. Electr. Syst. Levent Aksoy, Paulo F. Flores, José Monteiro
2014	A	`conf`	Optimization of design complexity in time-multiplexed constant multiplications. DATE Levent Aksoy, Paulo F. Flores, José Monteiro
2014	B	`conf`	Weakest Precondition Synthesis for Compiler Optimizations. VMCAI Nuno P. Lopes, José Monteiro
2013	—	`conf`	Automatic Equivalence Checking of UF+IA Programs. SPIN Nuno P. Lopes, José Monteiro
2013	J	`jnl`	Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. IEEE Trans. Very Large Scale Integr. Syst. Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro
2013	—	`conf`	Exploration of tradeoffs in the design of integer cosine transforms for image compression. ECCTD Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2013	—	`conf`	SIREN: a depth-first search algorithm for the filter design optimization problem. ACM Great Lakes Symposium on VLSI Levent Aksoy, Paulo F. Flores, José Monteiro
2013	—	`conf`	Standard CMOS voltage-mode QLUT using a clock boosting technique. NEWCAS Diogo Brito, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
2013	C	`conf`	Towards the least complex time-multiplexed constant multiplication. VLSI-SoC Levent Aksoy, Paulo F. Flores, José Monteiro
2012	—	`conf`	Design and characterization of a QLUT in a standard CMOS process. ICECS Diogo Brito, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
2012	A	`conf`	Design of low-complexity digital finite impulse response filters on FPGAs. DATE Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2012	—	`conf`	Efficient area and power multiplication part of FFT based on twiddle factor decomposition. ICECS Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis
2012	—	`conf`	Hardware pipelining of runtime-detected loops. SBCCI João Bispo, João M. P. Cardoso, José Monteiro
2012	J	`jnl`	High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. Integr. Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro
2012	A	`conf`	Multiple tunable constant multiplications: Algorithms and applications. ICCAD Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2012	J	`jnl`	Optimization Algorithms for the Multiplierless Realization of Linear Transforms. ACM Trans. Design Autom. Electr. Syst. Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2011	C	`conf`	A hybrid algorithm for the optimization of area and delay in linear DSP transforms. VLSI-SoC Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2011	—	`conf`	Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. ICECS Sidinei Ghissoni, Eduardo Costa, José Monteiro, Ricardo Reis
2011	—	`conf`	Design of low-power multiple constant multiplications using low-complexity minimum depth operations. ACM Great Lakes Symposium on VLSI Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2011	—	`conf`	Efficient shift-adds design of digit-serial multiple constant multiplications. ACM Great Lakes Symposium on VLSI Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro
2011	J	`jnl`	Finding the optimal tradeoff between area and delay in multiple constant multiplications. Microprocess. Microsystems Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2011	C	`conf`	Hardware implementation of a centroid-based localization algorithm for mobile sensor networks. ISCAS Leonardo L. de Oliveira, Gustavo Fernando Dessbesell, João B. Martins, José Monteiro
2011	J	`jnl`	Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. J. Low Power Electron. Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
2011	—	`conf`	Multiplierless Design of Linear DSP Transforms. VLSI-SoC (Selected Papers) Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2011	C	`conf`	Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. ISCAS Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro
2011	—	`conf`	Optimization of gate-level area in high throughput Multiple Constant Multiplications. ECCTD Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2010	A	`conf`	A new quaternary FPGA based on a voltage-mode multi-valued circuit. DATE Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro
2010	—	`conf`	An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. PATMOS Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro
2010	—	`conf`	CentroidM: a centroid-based localization algorithm for mobile sensor networks. SBCCI Leonardo Londero de Oliveira, João Baptista dos Santos Martins, Gustavo Fernando Dessbesell, José Monteiro
2010	C	`conf`	Design of low-complexity and high-speed digital Finite Impulse Response filters. VLSI-SoC Diego Jaccottet, Eduardo Costa, Levent Aksoy, Paulo F. Flores, José Monteiro
2010	—	`ed.`	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers PATMOS José Monteiro, Rene van Leuken
2010	J	`jnl`	Optimally Solving the MCM Problem Using Pseudo-Boolean Satisfiability CoRR Nuno P. Lopes, Levent Aksoy, Vasco Manquinho, José Monteiro
2010	C	`conf`	Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. DSD Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2010	—	`conf`	Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. ICECS Sidinei Ghissoni, Eduardo Costa, Cristiano Lazzari, José Monteiro, Levent Aksoy, Ricardo Reis
2010	C	`conf`	Voltage-mode quaternary FPGAs: An evaluation of interconnections. ISCAS Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro
2009	—	`ed.`	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers PATMOS Lars Svensson, José Monteiro
2009	—	`conf`	Parameter tuning in SVM-based power macro-modeling. ISQED António Gusmão, L. Miguel Silveira, José Monteiro
2009	C	`conf`	Power Macro-Modeling Using an Iterative LS-SVM Method. VLSI-SoC António Gusmão, Luís Miguel Silveira, José Monteiro
2008	J	`jnl`	Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2007	J	`jnl`	A new array architecture for signed multiplication using Gray encoded radix-2 Integr. Eduardo A. C. da Costa, José Monteiro, Sergio Bampi
2007	—	`conf`	Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. SiPS Levent Aksoy, Ece Olcay Günes, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2007	—	`conf`	Minimum number of operations under a general number representation for digital filter synthesis. ECCTD Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2007	A*	`conf`	Optimization of Area in Digital FIR Filters using Gate-Level Metrics. DAC Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2006	—	`conf`	ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. ICECS Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro
2006	—	`conf`	Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. SBCCI Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2006	A*	`conf`	Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. DAC Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2005	C	`conf`	A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. VLSI-SoC Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis
2005	A	`conf`	An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. ICCAD Paulo F. Flores, José Monteiro, Eduardo A. C. da Costa
2005	—	`conf`	Design of a radix-2 SBCCI Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro
2005	—	`conf`	Maximal sharing of partial terms in MCM under minimal signed digit representation. ECCTD Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro
2004	J	`jnl`	Power Estimation Using Probability Polynomials. Des. Autom. Embed. Syst. José C. Costa, Luís Miguel Silveira, Srinivas Devadas, José Monteiro
2003	—	`conf`	A New Pipelined Array Architecture for Signed Multiplication. SBCCI Eduardo A. C. da Costa, Sergio Bampi, José Monteiro
2002	—	`conf`	A New Architecture for 2's Complement Gray Encoded Array Multiplier. SBCCI Eduardo Costa, Sergio Bampi, José Monteiro
2002	C	`conf`	A New Architecture for Signed Radix-2m Pure Array Multipliers. ICCD Eduardo A. C. da Costa, Sergio Bampi, José Monteiro
2001	—	`conf`	Power Efficient Arithmetic Operand Encoding. SBCCI Eduardo Costa, Sergio Bampi, José Monteiro
2001	—	`conf`	Power Optimized Viterbi Decoder Implementation through Architectural Transforms. SBCCI João Portela, José Monteiro
2000	A	`conf`	Observability Analysis of Embedded Software for Coverage-Directed Validation. ICCAD José C. Costa, Srinivas Devadas, José Monteiro
2000	—	`conf`	Probabilistic Bottom-Up RTL Power Estimation. ISQED Ricardo Ferreira, Anne-Marie Trullemans, José C. Costa, José Monteiro
1999	—	`conf`	A probabilistic approach for RT-level power modeling. ICECS José C. Costa, José Monteiro, L. Miguel Silveira, Srinivas Devadas
1999	Misc	`conf`	Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. VLSI Design Paulo F. Flores, José C. Costa, Horácio C. Neto, José Monteiro, João Marques-Silva
1999	Misc	`conf`	CAD Techniques for Embedded System Design. VLSI Design Srinivas Devadas, Sharad Malik, José Monteiro, Luciano Lavagno
1999	—	`conf`	Integrating Dynamic Power Management in the Design Flow. VLSI Antônio Mota, Nuno Ferreira, Arlindo L. Oliveira, José Monteiro
1998	—	`conf`	Hardware support for CAN fault-tolerant communication. ICECS José Rufino, Nuno Pedrosa, José Monteiro, Paulo Veríssimo, Guilherme Arroz
1998	J	`jnl`	Power Estimation Under User-Specified Input Sequences and Programs. Integr. Comput. Aided Eng. José Monteiro, Srinivas Devadas
1998	J	`jnl`	Sequential logic optimization for low power using input-disabling precomputation architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José Monteiro, Srinivas Devadas, Abhijit Ghosh
1997	J	`jnl`	Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White
1996	J	`jnl`	Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. Very Large Scale Integr. Syst. Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
1996	A*	`conf`	Scheduling Techniques to Enable Power Management. DAC José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar
1996	J	`jnl`	Techniques for power estimation and optimization at the logic level: A survey. J. VLSI Signal Process. José Monteiro, Srinivas Devadas
1995	—	`conf`	Optimization of combinational and sequential logic circuits for low power using precomputation. ARVLSI José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh
1995	J	`jnl`	Power estimation methods for sequential logic circuits. IEEE Trans. Very Large Scale Integr. Syst. Chi-Ying Tsui, José Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
1995	—	`conf`	Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. ISLPD José Monteiro, Srinivas Devadas
1994	A*	`conf`	A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. DAC José Monteiro, Srinivas Devadas, Bill Lin
1994	Misc	`conf`	Bitwise Encoding of Finite State Machines. VLSI Design José Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto
1994	A	`conf`	Precomputation-based sequential logic optimization for low power. ICCAD Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
1994	J	`jnl`	Precomputation-based sequential logic optimization for low power. IEEE Trans. Very Large Scale Integr. Syst. Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
1993	A	`conf`	Retiming sequential circuits for low power. ICCAD José Monteiro, Srinivas Devadas, Abhijit Ghosh