José Manuel Cazeaux

12 papers A 1C 5Journal 4Unranked 1
YearRankTypeTitle / Venue / Authors
2014 J jnl
Clock Faults Induced Min and Max Delay Violations.
J. Electron. Test.
Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak
2009 J jnl
Accurate Linear Model for SET Critical Charge Estimation.
IEEE Trans. Very Large Scale Integr. Syst.
Daniele Rossi, José Manuel Cazeaux, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
2006 C conf
Can Clock Faults be Detected Through Functional Test?
DDECS
Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
2006 — —
Fault tolerant techniques for electronic systems implemented by nanometer technology.
José Manuel Cazeaux
2006 A conf
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects.
DATE
Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
2006 C conf
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.
IOLTS
Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
2005 J jnl
Novel on-chip circuit for jitter testing in high-speed PLLs.
IEEE Trans. Instrum. Meas.
José Manuel Cazeaux, Martin Omaña, Cecilia Metra
2005 C conf
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.
IOLTS
José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
2005 J jnl
Self-Checking Voter for High Speed TMR Systems.
J. Electron. Test.
José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
2005 — conf
The Other Side of the Timing Equation: a Result of Clock Faults.
DFT
Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
2004 C conf
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.
IOLTS
José Manuel Cazeaux, Martin Omaña, Cecilia Metra
2004 C conf
New High Speed CMOS Self-Checking Voter.
IOLTS
José Manuel Cazeaux, Daniele Rossi, Cecilia Metra