José M. Quintana

60 papers A 4B 1C 13Journal 15Unranked 27

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Clinical prediction rules for adverse evolution in patients with COVID-19 by the Omicron variant. Int. J. Medical Informatics Janire Portuondo-Jiménez, Irantzu Barrio, Pedro P. España, Julia García, Ane Villanueva, María Gascón, Lander Rodríguez, Nere Larrea, Susana García-Gutierrez, José M. Quintana
2021	J	`jnl`	Insights Into the Dynamics of Coupled VO IEEE Trans. Circuits Syst. II Express Briefs Juan Núñez, José M. Quintana, Maria José Avedillo, Manuel Jiménez Través, Aida Todri-Sanial, Elisabetta Corti, Siegfried F. Karg, Bernabé Linares-Barranco
2014	J	`jnl`	Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. IEEE Trans. Very Large Scale Integr. Syst. Juan Núñez, Maria J. Avedillo, José M. Quintana
2013	C	`conf`	Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. DSD Juan Núñez, Maria J. Avedillo, José M. Quintana
2013	J	`jnl`	Novel pipeline architectures based on Negative Differential Resistance devices. Microelectron. J. Juan Núñez, Maria J. Avedillo, José M. Quintana
2012	—	`conf`	Bifurcation diagrams in MOS-NDR frequency divider circuits. ICECS Juan Núñez, Maria J. Avedillo, José M. Quintana
2012	—	`conf`	Compact and Power Efficient MOS-NDR Muller C-Elements. DoCEIS Juan Núñez, Maria J. Avedillo, José M. Quintana
2012	—	`conf`	Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. PATMOS Juan Núñez, Maria J. Avedillo, José M. Quintana
2011	—	`conf`	Efficient realization of RTD-CMOS logic gates. ACM Great Lakes Symposium on VLSI Juan Núñez, Maria J. Avedillo, José M. Quintana
2010	C	`conf`	Evaluation of RTD-CMOS Logic Gates. DSD Juan Núñez, Maria J. Avedillo, José M. Quintana
2010	C	`conf`	Single phase MOS-NDR mobile networks. ISCAS Juan Núñez, Maria J. Avedillo, José M. Quintana
2009	C	`conf`	Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. ISCAS Juan Núñez, José M. Quintana, Maria J. Avedillo
2009	J	`jnl`	Operation Limits for RTD-Based MOBILE Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. José M. Quintana, Maria J. Avedillo, Juan Núñez, Héctor Pettenghi
2008	C	`conf`	A novel contribution to the RTD-based threshold logic family. ISCAS Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
2008	—	`conf`	Analysis of the critical rise time in MOBILE-based circuits. ICECS José M. Quintana, Maria J. Avedillo
2008	C	`conf`	Limits to a correct operation in RTD-based ternary inverters. ISCAS Juan Núñez, José M. Quintana, Maria J. Avedillo
2008	J	`jnl`	Using multi-threshold threshold gates in RTD-based logic design: A case study. Microelectron. J. Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
2007	—	`conf`	A quasi-differential quantizer based on SMOBILE. SBCCI Juan Núñez, José M. Quintana, Maria J. Avedillo
2007	—	`conf`	Correct operation in SMOBILE-based quasi-differential quantizers. ECCTD Juan Núñez, José M. Quintana, Maria J. Avedillo
2007	—	`conf`	Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. ISMVL Juan Núñez, José M. Quintana, Maria J. Avedillo
2007	C	`conf`	Non Return Mobile Logic Family. ISCAS Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
2007	—	`conf`	Operation limits in RTD-based ternary quantizers. ACM Great Lakes Symposium on VLSI Juan Núñez, José M. Quintana, Maria J. Avedillo
2006	C	`conf`	Design Guides for a Correct DC Operation in RTD-based Threshold Gates. DSD José M. Quintana, Maria J. Avedillo, Juan Núñez
2006	—	`conf`	Limits to a Correct Evaluation in RTD-based Ternary Inverters. ICECS Juan Núñez, José M. Quintana, Maria José Avedillo
2006	—	`conf`	Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. ICECS David Bol, Jean-Didier Legat, José M. Quintana, Maria José Avedillo
2006	C	`conf`	Self-latching operation limits for MOBILE circuits. ISCAS José M. Quintana, Maria J. Avedillo, Héctor Pettenghi
2006	J	`jnl`	Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. IEEE Trans. Circuits Syst. II Express Briefs Maria J. Avedillo, José M. Quintana, Héctor Pettenghi Roldán
2005	J	`jnl`	Analysis of frequency divider RTD circuits. IEEE Trans. Circuits Syst. I Regul. Pap. José M. Quintana, Maria J. Avedillo
2005	—	`conf`	Logic Models Supporting the Design of MOBILE-based RTD Circuits. ASAP Maria J. Avedillo, José M. Quintana, Héctor Pettenghi
2005	—	`conf`	Robust frequency divider based on resonant tunneling devices. ISCAS (3) Maria J. Avedillo, José M. Quintana, José L. Huertas
2004	J	`jnl`	A Practical Parallel Architecture for Stacks Filters. J. VLSI Signal Process. Maria J. Avedillo, José M. Quintana, Hamid El Alami, Antonio Jiménez-Calderón
2004	C	`conf`	A Threshold Logic Synthesis Tool for RTD Circuits. DSD Maria J. Avedillo, José M. Quintana
2004	J	`jnl`	Pass-transistor based implementations of threshold logic gates for WOS filtering. Microelectron. J. Maria J. Avedillo, José M. Quintana, Raúl Jiménez-Naharro
2004	—	`conf`	Programmable logic gate based on resonant tunnelling devices. ISCAS (3) José M. Quintana, Maria J. Avedillo, Héctor Pettenghi
2004	B	`conf`	RTD-based compact programmable gates. IJCNN José M. Quintana, Maria J. Avedillo, Héctor Pettenghi
2003	C	`conf`	Review of Capacitive Threshold Gate Implementations. ICANN Valeriu Beiu, Maria J. Avedillo, José M. Quintana
2003	—	`conf`	Review of Differential Threshold Gate Implementations. Neural Networks and Computational Intelligence Valeriu Beiu, José M. Quintana, Maria J. Avedillo
2003	J	`jnl`	VLSI implementations of threshold logic-a comprehensive survey. IEEE Trans. Neural Networks Valeriu Beiu, José M. Quintana, Maria J. Avedillo
2002	A	`conf`	An Encoding Technique for Low Power CMOS Implementations of Controllers. DATE Manuel Martínez, Maria J. Avedillo, José M. Quintana, H. Süß, Manfred Koegst
2002	J	`jnl`	COPAS: A New Algorithm for the Partial Input Encoding Problem. VLSI Design Manuel Martínez, Maria José Avedillo, José M. Quintana, José Luis Huertas
2002	—	`conf`	High-speed low-power logic gates using floating gates. ISCAS (5) Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda
2002	—	`conf`	Simple parallel weighted order statistic filter implementations. ISCAS (4) Maria J. Avedillo, José M. Quintana, Esther Rodríguez-Villegas
2002	—	`conf`	Simplified Reed-Muller expressions for residue threshold functions. ISCAS (4) José M. Quintana, Maria J. Avedillo, José L. Huertas
2002	—	`conf`	Threshold-logic-based design of compressors. ICECS José M. Quintana, Maria J. Avedillo, Esther Rodríguez-Villegas, Adoración Rueda
2001	J	`jnl`	Efficient Realization of a Threshold Voter for Self-Purging Redundancy. J. Electron. Test. José M. Quintana, Maria J. Avedillo, José Luis Huertas
2001	—	`conf`	Low-power logic styles for full-adder circuits. ICECS José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas
2001	—	`conf`	Practical low-cost CPL implementations threshold logic functions. ACM Great Lakes Symposium on VLSI José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas
2001	—	`conf`	Reed-Muller descriptions of symmetric functions. ISCAS (4) José M. Quintana, Maria J. Avedillo
2000	—	`conf`	Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy. SBCCI José M. Quintana, Maria J. Avedillo, Esther Rodríguez-Villegas, Adoración Rueda
2000	J	`jnl`	νMOS-based Sorter for Arithmetic Applications. VLSI Design Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda
1999	A	`conf`	An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. DATE Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas
1999	—	`conf`	vMOS-based sorters for multiplier implementations. ISCAS (1) Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda
1998	A	`conf`	A Dynamic Model for the State Assignment Problem. DATE Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas
1997	—	`conf`	A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. ED&TC Juan A. Prieto, Adoración Rueda, José M. Quintana, José Luis Huertas
1995	J	`jnl`	Constrained state assignment of easily testable FSMs. J. Electron. Test. Maria J. Avedillo, José M. Quintana, José Luis Huertas
1995	—	`conf`	Optimum PLA folding through boolean satisfiability. ASP-DAC José M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas
1994	C	`conf`	An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits. ISCAS Juan A. Prieto, José M. Quintana, Adoración Rueda, José L. Huertas
1993	C	`conf`	Easily Testable PLA-based FSMS. ISCAS Maria J. Avedillo, José M. Quintana, José L. Huertas
1990	—	`conf`	A new method for the state reduction of incompletely specified finite sequential machines. EURO-DAC Maria J. Avedillo, José M. Quintana, José Luis Huertas
1988	A	`conf`	A new method for the efficient state-assignment of PLA-based sequential machines. ICCAD José L. Huertas, José M. Quintana