José M. Mendías

32 papers A* 1A 9C 4Misc 1Journal 10Unranked 7
YearRankTypeTitle / Venue / Authors
2024 J jnl
Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens.
Borja Morcillo, Daniel Báscones, Carlos González, José M. Mendías, Daniel Mozos
2013 J jnl
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths.
Integr.
Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida
2012 J jnl
Multispeculative Addition Applied to Datapath Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, José M. Mendías, María C. Molina
2011 A conf
Power optimization in heterogenous datapaths.
DATE
Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida
2009 J jnl
Performance-driven scheduling of behavioural specifications.
Integr.
María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, José M. Mendías
2007 J jnl
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
CoRR
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
2006 A conf
Pre-synthesis optimization of multiplications to improve circuit performance.
DATE
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
2005 — conf
Arrival time aware scheduling to minimize clock cycle length.
ASP-DAC
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
2005 A conf
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis.
DATE
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
2005 J jnl
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications.
J. VLSI Signal Process.
Marc Leeman, David Atienza, Geert Deconinck, Vincenzo De Florio, José M. Mendías, Chantal Ykman-Couvreur, Francky Catthoor, Rudy Lauwereins
2005 — conf
Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications.
WWIC
Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis
2004 A conf
Behavioural Bitwise Scheduling Based on Computational Effort Balancing.
DATE
María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
2004 — conf
Behavioural Scheduling to Balance the Bit-Level Computational Effort.
ISVLSI
María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
2004 J jnl
Memory-access-aware data structure transformations for embedded software with dynamic data accesses.
IEEE Trans. Very Large Scale Integr. Syst.
Edgar G. Daylight, David Atienza, Arnout Vandecappelle, Francky Catthoor, José M. Mendías
2003 J jnl
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources.
J. Syst. Archit.
María C. Molina, José M. Mendías, Román Hermida
2003 — conf
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.
PATMOS
María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
2003 A conf
High-Level Allocation to Minimize Internal Hardware Wastage.
DATE
María C. Molina, José M. Mendías, Román Hermida
2002 J jnl
A global approach to improve conditional hardware reuse in high-level synthesis.
J. Syst. Archit.
Olga Peñalba, José M. Mendías, Román Hermida
2002 J jnl
A study about the efficiency of formal high-level synthesis applied to verification.
Integr.
José M. Mendías, Román Hermida, Olga Peñalba
2002 C conf
Bit-Level Allocation of Multiple-Precision Specifications.
DSD
María C. Molina, José M. Mendías, Román Hermida
2002 A conf
Bit-level scheduling of heterogeneous behavioural specifications.
ICCAD
María C. Molina, José M. Mendías, Román Hermida
2002 C conf
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis.
DSD
José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba
2002 A* conf
High-level synthesis of multiple-precision circuitsindependent of data-objects length.
DAC
María C. Molina, José M. Mendías, Román Hermida
2002 A conf
Maximizing Conditonal Reuse by Pre-Synthesis Transformations.
DATE
Olga Peñalba, José M. Mendías, Román Hermida
2002 A conf
Multiple-Precision Circuits Allocation Independent of Data-Objects Length.
DATE
María C. Molina, José M. Mendías, Román Hermida
2002 C conf
Optimization of Equational Specifications Using Genetic Techniques.
DSD
Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida
2002 C conf
Source Code Transformation to Improve Conditional Hardware Reuse.
DSD
Olga Peñalba, José M. Mendías, Román Hermida
2000 — conf
Execution Condition Analysis in High Level Synthesis: A Unified Approach.
ISSS
Olga Peñalba, José M. Mendías, María C. Molina
1999 — conf
A Unified Algorithm for Mutual Exclusiveness Identification.
EUROMICRO
Olga Peñalba, José M. Mendías, Román Hermida
1998 A conf
Correct High-Level Synthesis: a Formal Perspective.
DATE
José M. Mendías, Román Hermida
1997 Misc conf
Formal Techniques for Hardware Allocation.
VLSI Design
José M. Mendías, Román Hermida, Milagros Fernández
1996 — conf
Algebraic Support for Transformational Hardware Allocation.
ED&TC
José M. Mendías, Román Hermida, Milagros Fernández