José M. Llabería

40 papers A* 7A 3B 2C 1Journal 12Unranked 15

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Forecasting lifetime and performance of a novel NVM last-level cache with compression. CoRR Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
2022	J	`jnl`	L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. CoRR Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
2021	J	`jnl`	Near-optimal replacement policies for shared caches in multicore processors. J. Supercomput. Javier Díaz, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José M. Llabería
2019	J	`jnl`	ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distributed Comput. Javier Díaz, Teresa Monreal, Pablo Ibáñez, José M. Llabería, Víctor Viñals
2013	A*	`conf`	The reuse cache: downsizing the shared last-level cache. MICRO Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José M. Llabería
2011	J	`jnl`	Filtering directory lookups in CMPs. Microprocess. Microsystems Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería
2010	C	`conf`	Filtering Directory Lookups in CMPs. DSD Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería
2006	—	`conf`	Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par Agustín De Dios Hernández, Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José M. Llabería
2003	J	`jnl`	A Cost-Effective Implementation of Multilevel Tiling. IEEE Trans. Parallel Distributed Syst. Marta Jiménez, José M. Llabería, Agustín Fernández
2002	J	`jnl`	Register tiling in nonrectangular iteration spaces. ACM Trans. Program. Lang. Syst. Marta Jiménez, José M. Llabería, Agustín Fernández
2000	B	`conf`	Modeling load address behaviour through recurrences. ISPASS Luis M. Ramos, Pablo E. Ibáñez, Víctor Viñals, José M. Llabería
2000	A*	`conf`	On the Performance of Hand vs. Automatically Optimized Numerical Codes. HPCA Marta Jiménez, José M. Llabería, Agustín Fernández
2000	—	`conf`	Two-Level Address Storage and Address Prediction (Research Note). Euro-Par Enric Morancho, José M. Llabería, Àngel Olivé
1999	—	`conf`	Looking at History to Filter Allocations in Prediction Tables. IEEE PACT Enric Morancho, José M. Llabería, Àngel Olivé
1999	J	`jnl`	Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems. IEEE Trans. Computers Anna M. del Corral, José M. Llabería
1998	A	`conf`	A General Algorithm for Tiling the Register Level. International Conference on Supercomputing Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho
1998	—	`conf`	New Access Order to Reduce Inter-Vector-Conflicts. VECPAR Anna M. del Corral, José M. Llabería
1998	A*	`conf`	Performance Evaluation of Tiling for the Register Level. HPCA Marta Jiménez, José M. Llabería, Agustín Fernández
1998	—	`conf`	Split Last-Address Predictor. IEEE PACT Enric Morancho, José M. Llabería, Àngel Olivé
1996	—	`conf`	A Unified Transformation Technique for Multilevel Blocking. Euro-Par, Vol. I Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho
1996	—	`conf`	Increasing the Effective Memory Bandwidth in Multivector Processors. EUROMICRO Anna M. del Corral, José M. Llabería
1996	A	`conf`	Reducing Inter-Vector-Conflicts in Complex Memory Systems. International Conference on Supercomputing Anna M. del Corral, José M. Llabería
1995	—	`conf`	Access order to avoid inter-vector-conflicts in complex memory systems. IPPS Anna M. del Corral, José M. Llabería
1995	J	`jnl`	Loop Transformation Using Nonunimodular Matrices. IEEE Trans. Parallel Distributed Syst. Agustín Fernández, José M. Llabería, Miguel Valero-García
1994	—	`conf`	Out-of-order access to vector elements in order to reduce conflicts in vector processors. SPDP Anna M. del Corral, José M. Llabería
1993	J	`jnl`	Reducing Branch Delay to Zero in Pipelined Processors. IEEE Trans. Computers Antonio González, José M. Llabería
1992	J	`jnl`	Evaluation of A + B = K Conditions Without Carry Propagation. IEEE Trans. Computers Jordi Cortadella, José M. Llabería
1992	A*	`conf`	Increasing the Number of Strides for Conflict-Free Vector Access. ISCA Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro
1992	—	`conf`	Scheduling partitions in systolic algorithms. ASAP Alvaro Suárez, José M. Llabería, Agustín Fernández
1991	—	`conf`	Balanced Loop Partitioning Using GTS. LCPC Jesús Labarta, Eduard Ayguadé, Jordi Torres, Mateo Valero, José M. Llabería
1991	—	`conf`	Interleaving Partitions of Systolic Algorithms for Programming Distributed Memory Multiprocessors. EDMCC Agustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García
1991	—	`conf`	On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. EDMCC Jordi Torres, Eduard Ayguadé, Jesús Labarta, José M. Llabería, Mateo Valero
1991	—	`conf`	Transformation of systolic algorithms for interleaving partitions. ASAP Agustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García
1990	—	`conf`	Implementation of systolic algorithms using pipelined functional units. ASAP Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero
1989	A	`conf`	Instruction fetch unit for parallel execution of branch instructions. ICS Antonio González, José M. Llabería
1989	A*	`conf`	Systematic Hardware Adaptation of Systolic Algorithms. ISCA Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero
1987	J	`jnl`	Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors. Computer Juan J. Navarro, José M. Llabería, Mateo Valero
1986	A*	`conf`	Computing Size-Independent Matrix Problems on Systolic Array Processors. ISCA Juan J. Navarro, José M. Llabería, Mateo Valero
1986	B	`conf`	Solving Matrix Problems with No Size Restriction on a Systolic Array Processor. ICPP Juan J. Navarro, José M. Llabería, Mateo Valero
1985	A*	`conf`	Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. ISCA José M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta