José Luís Güntzel

59 papers A 1B 1C 7Misc 1Journal 9Unranked 40

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Parallel JPEG Pleno Baseline Block-Based Profile Light Field Codec Using OpenMP. IEEE Trans. Circuits Syst. I Regul. Pap. André Filipe da Silva Fernandes, Ismael Seidel, Leonardo de Sousa Marques, Arthur Scarpatto Rodrigues, José Luís Güntzel
2025	—	`conf`	A Parallel JPEG Pleno Baseline Block-Based Profile Light Field Encoder Using OpenMP. LASCAS Ismael Seidel, André Filipe da Silva Fernandes, José Luís Güntzel
2025	J	`jnl`	Asymmetric Multi-Layer Compression: Decoupling Inter-Layer Coding Dependencies With a Learned Model. IEEE Access Luiz Henrique Cancellier, André Beims Bräscher, Ismael Seidel, Mateus Grellert, Luís Alberto da Silva Cruz, José Luís Güntzel
2025	J	`jnl`	Eh-DRVP: Combining placement and global routing data in a hyper-image-based DRV predictor. Integr. Sheiny Fabre Almeida, Renan Netto, Tiago Augusto Fontana, Erfan Aghaeekiasaraee, Upma Gandhi, Aysa Fakheri Tabrizi, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt
2025	—	`conf`	GRCMO: Global Routing Optimization by Median-Based Cell Movement. LASCAS Arthur Lourenco, Felipe Savi, Felipe Nascimento, Erfan Aghaeekiasaraee, Upma Gandhi, Renan Netto, Laleh Behjat, Tiago Augusto Fontana, José Luís Güntzel
2025	—	`conf`	Markov Modeling of Video Coding Prediction Residue for Transform Hardware Power Analysis. NewCAS João Marcos Marqueti, Gustavo Russi, Ismael Seidel, José Luís Güntzel
2024	—	`conf`	A Dual-Kernel Size-Configurable Gaussian Filter Architecture. SBCCI Marcio Monteiro, Ismael Seidel, José Luís Güntzel, Mateus Grellert, Leonardo Bandeira Soares, Cristina Meinhardt
2024	J	`jnl`	ILPGRC: ILP-Based Global Routing Optimization With Cell Movements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tiago Augusto Fontana, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, Laleh Behjat, José Luís Güntzel
2023	—	`conf`	A New Approach to Video Coding Leveraging Hybrid Coding and Video Frame Interpolation. SBCCI André Beims Bräscher, Gabriela Furtado Da Silveira, Luiz Henrique Cancellier, Ismael Seidel, Mateus Grellert, José Luís Güntzel
2023	J	`jnl`	CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes. ACM Trans. Design Autom. Electr. Syst. Erfan Aghaeekiasaraee, Aysa Fakheri Tabrizi, Tiago Augusto Fontana, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, José Luís Güntzel, David T. Westwick, Laleh Behjat
2023	—	`conf`	Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME. SBCCI Vanio Rodrigues Filho, Ismael Seidel, Nicole Citadin, Marcio Monteiro, Mateus Grellert, José Luís Güntzel
2022	J	`jnl`	Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, Laleh Behjat, José Luís Güntzel
2022	—	`conf`	Autoencoder Model Exploration for Multi-Layer Video Compression. EUVIP Luiz Henrique Cancellier, Mateus Grellert, José Luís Güntzel, Luís Alberto da Silva Cruz
2022	—	`conf`	E-RVP: An Initial Design Rule Violation Predictor Using Placement Information. ICECS 2022 Sheiny Fabre Almeida, Aysa Fakheri Tabrizi, Erfan Aghaeekiasaraee, Renan Netto, Tiago Augusto Fontana, Upma Gandhi, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt
2022	—	`conf`	Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection. LASCAS Marcio Monteiro, Ismael Seidel, Mateus Grellert, José Luís Güntzel, Leonardo Bandeira Soares, Cristina Meinhardt
2022	C	`conf`	Routability-Driven Detailed Placement Using Reinforcement Learning. VLSI-SoC Sheiny Fabre Almeida, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt
2021	C	`conf`	Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders. ISCAS Marcio Monteiro, Pedro Aquino Silva, Ismael Seidel, Mateus Grellert, Leonardo Bandeira Soares, José Luís Güntzel, Cristina Meinhardt
2021	C	`conf`	Hardware-Friendly Search Patterns for the Versatile Video Coding Fractional Motion Estimation. MMSP Vanio Rodrigues Filho, Marcio Monteiro, Ismael Seidel, Mateus Grellert, José Luís Güntzel
2021	—	`conf`	ILP-Based Global Routing Optimization with Cell Movements. ISVLSI Tiago Augusto Fontana, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat, José Luís Güntzel
2021	Misc	`conf`	Relying on a Rate Constraint to Reduce Motion Estimation Complexity. ICASSP Gabriel B. Sant'Anna, Luiz Henrique Cancellier, Ismael Seidel, Mateus Grellert, José Luís Güntzel
2021	C	`conf`	SAD or SATD? How the Distortion Metric Impacts a Fractional Motion Estimation VLSI Architecture. MMSP Ismael Seidel, Vanio Rodrigues Filho, Mateus Grellert, Luciano Volcan Agostini, José Luís Güntzel
2020	J	`jnl`	Guest Editors' Introduction: SBCCI 2018. IEEE Des. Test Michael Hübner, José Luís Güntzel
2020	—	`conf`	Standalone Rate-Distortion FME Architecture. SBCCI Vanio Rodrigues Filho, Marcio Monteiro, Ismael Seidel, Mateus Grellert, José Luís Güntzel
2019	J	`jnl`	Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse. IEEE Trans. Circuits Syst. I Regul. Pap. Ismael Seidel, Marcio Monteiro, Bruno Bonotto, Luciano Volcan Agostini, José Luís Güntzel
2019	—	`conf`	How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization. ISPD Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, José Luís Güntzel
2018	—	`conf`	A Domain-specific Language for Automated Fault Injection in SystemC Models. ICECS Douglas Lohmann, Alexis Huf, Djones Lettnin, Frank Siqueira, José Luís Güntzel
2018	C	`conf`	Coding- and Energy-Efficient FME Hardware Design. ISCAS Ismael Seidel, Vanio Rodrigues Filho, Luciano Volcan Agostini, José Luís Güntzel
2018	—	`conf`	Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning. SBCCI Sheiny Fabre, José Luís Güntzel, Laércio Lima Pilla, Renan Netto, Tiago Fontana, Vinicius S. Livramento
2018	—	`conf`	On HEVC Robustness to Integer Motion Estimation Pruning. ICECS Luiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel
2018	—	`conf`	On the calculation reuse in hadamard-based SATD. LASCAS Marcio Monteiro, Ismael Seidel, José Luís Güntzel
2017	—	`conf`	Block matching hardware architecture for SATD-based successive elimination. SBCCI Luiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel
2017	—	`conf`	Exploiting cache locality to speedup register clustering. SBCCI Tiago Augusto Fontana, Sheiny Almeida, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Laércio Lima Pilla, José Luís Güntzel
2017	—	`conf`	How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library. ISPD Tiago Fontana, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Sheiny Almeida, Laércio Lima Pilla, José Luís Güntzel
2017	—	`conf`	Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE. SBCCI André Beims Bräscher, Ismael Seidel, José Luís Güntzel
2016	J	`jnl`	Clock-Tree-Aware Incremental Timing-Driven Placement. ACM Trans. Design Autom. Electr. Syst. Vinicius S. Livramento, Renan Netto, Chrystian Guth, José Luís Güntzel, Luiz Cláudio Villar dos Santos
2016	—	`conf`	Coarse grain partial distortion elimination for Hadamard ME in HEVC. ICECS Ismael Seidel, José Luís Güntzel, Luciano Volcan Agostini
2016	—	`conf`	Evaluating the impact of circuit legalization on incremental optimization techniques. SBCCI Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel
2016	—	`conf`	Exploiting parallelism to speed up circuit legalization. ICECS Renan Netto, Chrystian Guth, Vinicius S. Livramento, Márcio Castro, Laércio Lima Pilla, José Luís Güntzel
2016	—	`conf`	Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees. ISVLSI Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel
2015	—	`conf`	Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency. PATMOS Ismael Seidel, André Beims Bräscher, José Luís Güntzel
2015	—	`conf`	Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression. ISPD Chrystian Guth, Vinicius S. Livramento, Renan Netto, Renan Fonseca, José Luís Güntzel, Luiz C. V. dos Santos
2014	—	`conf`	Energy-Efficient Hadamard-Based SATD Architectures. SBCCI Luiz Henrique Cancellier, André Beims Bräscher, Ismael Seidel, José Luís Güntzel
2013	—	`conf`	A low-power configurable VLSI architecture for sum of absolute differences calculation. LASCAS Ismael Seidel, Bruno George de Moraes, José Luís Güntzel
2013	A	`conf`	Fast and efficient lagrangian relaxation-based discrete gate sizing. DATE Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann
2013	—	`conf`	On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation. SBCCI Ismael Seidel, Bruno George de Moraes, André Beims Bräscher, José Luís Güntzel
2013	—	`conf`	VLSI architectures for Digital Modulation Classification using Support Vector Machines. LASCAS Edson Sorato, Renan Netto, Pedro Michel, José Luís Güntzel, Adalbery R. Castro, Aldebaro Klautau
2012	—	`conf`	Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization. ICECS Vinicius dos S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann
2011	—	`conf`	A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design. ICECS Jucemar Monteiro, José Luís Güntzel, Luciano Volcan Agostini
2011	C	`conf`	An energy-efficient 8×8 2-D DCT VLSI architecture for battery-powered portable devices. ISCAS Vinicius S. Livramento, Bruno George de Moraes, Brunno Abner Machado, José Luís Güntzel
2007	B	`conf`	RIC Fast Adder and its Set Tolerant Implementation in FPGAs. FPL Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel
2006	—	`conf`	High throughput architecture for H.264/AVC forward transforms block. ACM Great Lakes Symposium on VLSI Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Leandro Rosa, José Luís Güntzel, Ivan Saraiva Silva
2006	C	`conf`	High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard. ISCAS Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, José Luís Güntzel, Ivan Saraiva Silva, Sergio Bampi
2005	—	`conf`	Incremental timing optimization for automatic layout generation. ISCAS (4) Cristiano Santos, Daniel Lima Ferrão, Ricardo Reis, José Luís Güntzel
2003	—	`conf`	A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits. VLSI-SoC (Selected Papers) Cristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis
2002	—	`conf`	A Comparison Between Testability Measures Applied to Complex Gates. LATW José Luís Güntzel, Gustavo Wilke, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis
2002	—	`conf`	Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing. SBCCI Gustavo Wilke, José Luís Güntzel, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis
2001	—	`conf`	A Timed Calculus for ATG-Based Timing Analysis with Complex Gates. LATW José Luís Güntzel, Ana Cristina Medina Pinto, Ricardo Reis
2000	—	`conf`	ATG-Based Timing Analysis of Circuits Containing Complex Gates. SBCCI José Luís Güntzel, Ana Cristina Medina Pinto, Eduardo D'Avila, Ricardo Reis
1998	—	`conf`	An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays. SBCCI José Luís Güntzel, Ana Cristina Medina Pinto, Fernando Moraes, Ricardo Reis