José Luis Rosselló

40 papers A 7B 5Misc 1Journal 19Unranked 8
YearRankTypeTitle / Venue / Authors
2018 J jnl
A Stochastic Spiking Neural Network for Virtual Screening.
IEEE Trans. Neural Networks Learn. Syst.
Antoni Morro, Vicent Canals, Antoni Oliver, Miquel L. Alomar, Fabio Galán-Prado, Pedro J. Ballester, José Luis Rosselló
2016 J jnl
Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective.
Commun. Nonlinear Sci. Numer. Simul.
Joan Barceló, José Luis Rosselló, Sebastià A. Bota, Jaume Segura, Jaume Verd
2015 J jnl
Digital Implementation of a Single Dynamical Node Reservoir Computer.
IEEE Trans. Circuits Syst. II Express Briefs
Miquel L. Alomar, Miguel C. Soriano, Miguel Angel Escalona-Morán, Vincent Canals, Ingo Fischer, Claudio R. Mirasso, José Luis Rosselló
2015 — conf
Stochastic-Based Implementation of Reservoir Computers.
IWANN (2)
Miquel L. Alomar, Vincent Canals, Víctor Martínez-Moll, José Luis Rosselló
2014 — conf
Low-cost hardware implementation of Reservoir Computers.
PATMOS
Miquel L. Alomar, Vicent Canals, Víctor Martínez-Moll, José Luis Rosselló
2014 B conf
Stochastic Spiking Neural Networks at the EDGE of CHAOS.
IJCNN
José Luis Rosselló, Vicent Canals, Antoni Oliver, Antoni Morro
2014 J jnl
Studying the Role of Synchronized and Chaotic Spiking Neural Ensembles in Neural Information Processing.
Int. J. Neural Syst.
José Luis Rosselló, Vicent Canals, Antoni Oliver, Antoni Morro
2012 J jnl
Hardware Implementation of Stochastic Spiking Neural Networks.
Int. J. Neural Syst.
José Luis Rosselló, Vincent Canals, Antoni Morro, Antoni Oliver
2012 B conf
Probabilistic-based neural network implementation.
IJCNN
José Luis Rosselló, Vincent Canals, Antoni Morro
2012 J jnl
Stochastic-Based Pattern Recognition Analysis
CoRR
Vincent Canals, Antoni Morro, José Luis Rosselló
2010 J jnl
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination.
IEEE Trans. Circuits Syst. II Express Briefs
Gabriel Torrens, Bartomeu Alorda, Salvador Barceló, José Luis Rosselló, Sebastià A. Bota, Jaume Segura
2010 B conf
Hardware implementation of stochastic-based Neural Networks.
IJCNN
José Luis Rosselló, Vincent Canals, Antoni Morro
2010 J jnl
Stochastic-based pattern-recognition analysis.
Pattern Recognit. Lett.
Vincent Canals, Antoni Morro, José Luis Rosselló
2009 J jnl
Chaos-Based Mixed Signal Implementation of Spiking Neurons.
Int. J. Neural Syst.
José Luis Rosselló, Vincent Canals, Antoni Morro, Jaume Verd
2009 — conf
Practical Hardware Implementation of Self-configuring Neural Networks.
ISNN (3)
José Luis Rosselló, Vincent Canals, Antoni Morro, Ivan de Paúl
2009 — conf
Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis.
ICANN (1)
José Luis Rosselló, Ivan de Paúl, Vincent Canals, Antoni Morro
2008 J jnl
A simple CMOS chaotic integrated circuit.
IEICE Electron. Express
José Luis Rosselló, Vincent Canals, Ivan de Paúl, Sebastià A. Bota, Antoni Morro
2008 J jnl
Self-configuring spiking neural networks.
IEICE Electron. Express
José Luis Rosselló, Ivan de Paúl, Vincent Canals
2008 B conf
Using stochastic logic for efficient pattern recognition analysis.
IJCNN
José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura
2007 J jnl
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
CoRR
José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
2007 A conf
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs.
DATE
José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
2007 J jnl
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs
CoRR
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
2006 B conf
A Fully CMOS Low-Cost Chaotic Neural Network.
IJCNN
José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura
2006 A conf
A compact model to identify delay faults due to crosstalk.
DATE
José Luis Rosselló, Jaume Segura
2006 J jnl
Impact of Thermal Gradients on Clock Skew and Testing.
IEEE Des. Test Comput.
Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura
2006 — conf
Leakage Power Characterization Considering Process Variations.
PATMOS
José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
2006 Misc conf
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?.
VTS
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
2005 A conf
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs.
DATE
José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
2005 J jnl
A compact gate-level energy and delay model of dynamic CMOS gates.
IEEE Trans. Circuits Syst. II Express Briefs
José Luis Rosselló, Carol de Benito, Jaume Segura
2005 — conf
Compact Static Power Model of Complex CMOS Gates.
PATMOS
José Luis Rosselló, Sebastià A. Bota, Jaume Segura
2005 A conf
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs.
DATE
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
2004 A conf
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk.
DATE
José Luis Rosselló, Jaume Segura
2004 J jnl
An analytical charge-based compact delay model for submicrometer CMOS inverters.
IEEE Trans. Circuits Syst. I Regul. Pap.
José Luis Rosselló, Jaume A. Segura
2004 A conf
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism.
ITC
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi
2003 — conf
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates.
PATMOS
José Luis Rosselló, Jaume Segura
2003 J jnl
Structural RFIC device testing through built-in thermal monitoring.
IEEE Commun. Mag.
Josep Altet, Antonio J. Rubio, José Luis Rosselló, Jaume Segura
2002 — conf
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers.
PATMOS
José Luis Rosselló, Jaume Segura
2002 J jnl
Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
José Luis Rosselló, Jaume Segura
2001 A conf
Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization.
ICCAD
José Luis Rosselló, Jaume Segura
1998 J jnl
A variable threshold voltage inverter for CMOS programmable logic circuits.
IEEE J. Solid State Circuits
Jaume Segura, José Luis Rosselló, J. Morra, H. Sigg