José Luis Núñez-Yáñez

30 papers B 6C 1Journal 12Unranked 10
YearRankTypeTitle / Venue / Authors
2022 — conf
Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network.
ARC
Minxuan Kong, José Luis Núñez-Yáñez
2022 C conf
Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks.
DSD
Minxuan Kong, Kris Nikov, José Luis Núñez-Yáñez
2020 J jnl
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2018 J jnl
Dynamic Energy Management of FPGA Accelerators in Embedded Systems.
ACM Trans. Embed. Comput. Syst.
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2017 B conf
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis.
FPL
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2017 — conf
Pipelined Streaming Computation of Histogram in FPGA OpenCL.
PARCO
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2016 — conf
CPCIe: A compression-enabled PCIe core for energy and performance optimization.
NORCAS
Mohd Amiruddin Zainol, José Luis Núñez-Yáñez
2016 J jnl
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling.
IEEE Trans. Computers
José Luis Núñez-Yáñez, Mohammad Hosseinabady, Arash Beldachi
2016 — conf
Energy proportional computing with OpenCL on a FPGA-based overlay architecture.
NORCAS
Awais Hussain Sani, José Luis Núñez-Yáñez
2015 J jnl
Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs.
IEEE Trans. Computers
José Luis Núñez-Yáñez
2015 J jnl
Biologically compatible neural networks with reconfigurable hardware.
Microprocess. Microsystems
Juan Carlos Moctezuma, Joseph P. McGeehan, José Luis Núñez-Yáñez
2015 B conf
Energy optimization of FPGA-based stream-oriented computing with power gating.
FPL
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2015 B conf
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices.
FPL
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2014 J jnl
Bayesian Video Super-Resolution With Heavy-Tailed Prior Models.
IEEE Trans. Circuits Syst. Video Technol.
Jin Chen, José Luis Núñez-Yáñez, Alin Achim
2014 — conf
Neuron Dynamics of Two-compartment Traub Model for Hardware-based Emulation.
IJCCI (NCTA)
Juan Carlos Moctezuma, José Luis Núñez-Yáñez, Joseph P. McGeehan
2014 B conf
Run-time power gating in hybrid ARM-FPGA devices.
FPL
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2013 J jnl
Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic.
IEEE Trans. Computers
Yiwei Zhang, Joseph McGeehan, Edward Regan, Stephen Kelly, José Luis Núñez-Yáñez
2013 — conf
Numerically efficient and biophysically accurate neuroprocessing platform.
ReConFig
Juan Carlos Moctezuma, Joseph McGeehan, José Luis Núñez-Yáñez
2012 J jnl
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform.
ACM Trans. Reconfigurable Technol. Syst.
Atukem Nabina, José Luis Núñez-Yáñez
2012 J jnl
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding.
IEEE Trans. Very Large Scale Integr. Syst.
José Luis Núñez-Yáñez, Atukem Nabina, Eddie Hung, George Vafiadis
2012 J jnl
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation.
IET Comput. Digit. Tech.
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2012 J jnl
Lossless video compression based on backward adaptive pixel-based fast motion estimation.
Signal Process. Image Commun.
Xiaolin Chen, Nishan Canagarajah, José Luis Núñez-Yáñez, Raffaele Vitulli
2012 J jnl
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles.
IET Comput. Digit. Tech.
Mohammad Hosseinabady, José Luis Núñez-Yáñez
2010 — conf
Task Dispersal Measurement in Dynamic Reconfigurable NoCs.
ISVLSI
Mohammad Hosseinabady, José Luis Núñez-Yáñez, Antonio Marcello Coppola
2009 B conf
A toolset for the analysis and optimization of motion estimation algorithms and processors.
FPL
Trevor Spiteri, George Vafiadis, José Luis Núñez-Yáñez
2009 — conf
Adaptive stochastic routing in fault-tolerant on-chip networks.
NOCS
Wei Song, Doug A. Edwards, José Luis Núñez-Yáñez, Sohini Dasgupta
2008 B conf
A configurable and programmable motion estimation processor for the H.264 video codec.
FPL
José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras
2008 — conf
Statistical Lossless Compression of Space Imagery and General Data in a Reconfigurable Architecture.
AHS
José Luis Núñez-Yáñez, Xiaolin Chen, Nishan Canagarajah, Raffaele Vitulli
2007 — conf
Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding.
SoCC
Xiaolin Chen, Nishan Canagarajah, José Luis Núñez-Yáñez, Raffaele Vitulli
2001 — —
Gbit/second lossless data compression hardware.
José Luis Núñez-Yáñez