José Luis Neves

23 papers A* 3A 3C 3Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2018 J jnl
IBM z14 design methodology enhancements in the 14-nm technology node.
IBM J. Res. Dev.
Christopher J. Berry, James D. Warnock, John Badar, Dean G. Bair, Erwin Behnen, Brian Bell, Alper Buyuktosunoglu, Chris Cavitt, Pierce Chuang, Ofer Geva, Dina Hamid, John Isakson, Preetham Lobo, Frank Malgioglio, Guenter Mayer, José Luis Neves, Thomas Strach, Jesse Surprise, Christos Vezyrtzis, Tobias Webel, David Wolpert
2006 A conf
Parallelizing post-placement timing optimization.
IPDPS
Jiyoun Kim, Marios C. Papaefthymiou, José Luis Neves
2002 J jnl
Inductance Effects in RLC Trees.
J. Circuits Syst. Comput.
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
2001 J jnl
Exploiting the on-chip inductance in high-speed clock distribution networks.
IEEE Trans. Very Large Scale Integr. Syst.
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
2001 J jnl
Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
2001 — conf
Steiner tree optimization for buffers. Blockages and bays.
ISCAS (5)
Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
2000 C conf
Buffer Library Selection.
ICCD
José Luis Neves, Stephen T. Quay
2000 J jnl
Equivalent Elmore delay for RLC trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 A* conf
Equivalent Elmore Delay for
DAC
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 J jnl
Figures of merit to characterize the importance of on-chip inductance.
IEEE Trans. Very Large Scale Integr. Syst.
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 — conf
Inductance Effects in RLC Trees.
Great Lakes Symposium on VLSI
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 A conf
Repeater insertion in tree structured inductive interconnect.
ICCAD
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 — conf
Signal waveform characterization in RLC trees.
ISCAS (6)
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998 J jnl
Automated Synthesis of Skew-Based Clock Distribution Networks.
VLSI Design
José Luis Neves, Eby G. Friedman
1998 — conf
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.
Great Lakes Symposium on VLSI
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998 A* conf
Figures of Merit to Characterize the Importance of On-Chip Inductance.
DAC
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998 A conf
Power dissipated by CMOS gates driving lossless transmission lines.
ISLPED
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998 — conf
Transient power in CMOS gates driving LC transmission lines.
ICECS
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1997 J jnl
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.
J. VLSI Signal Process.
José Luis Neves, Eby G. Friedman
1996 J jnl
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew.
IEEE Trans. Very Large Scale Integr. Syst.
José Luis Neves, Eby G. Friedman
1996 A* conf
Optimal Clock Skew Scheduling Tolerant to Process Variations.
DAC
José Luis Neves, Eby G. Friedman
1995 C conf
Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks.
ISCAS
José Luis Neves, Eby G. Friedman
1994 C conf
Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew.
ISCAS
José Luis Neves, Eby G. Friedman