José Luis Imaña

37 papers A 1B 3C 2Misc 3Journal 23Unranked 5
YearRankTypeTitle / Venue / Authors
2025 — conf
ARM Architecture Optimizations for Line-Rate PQC Communications.
ONDM
Abraham Cano Aguilera, Idelfonso Tafur Monroy, J. J. Vegas Olmos, José Luis Imaña
2025 — conf
First Demonstration of 200 Gbps Regime Line-Rate Quantum-Secure MACsec Optical Links Using Commodity Hardware Offloads.
OFC
Abraham Cano Aguilera, Carlos Rubio Garcia, Daniel C. Lawo, Idelfonso Tafur Monroy, José Luis Imaña, J. J. Vegas Olmos
2024 J jnl
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration.
IEEE Trans. Circuits Syst. II Express Briefs
José Luis Imaña, Luis Piñuel, Yao-Ming Kuo, Oscar Ruano, Francisco Garcia-Herrero
2024 J jnl
Falcon/Kyber and Dilithium/Kyber Network Stack on Nvidia's Data Processing Unit Platform.
IEEE Access
Daniel C. Lawo, Raphael Frantz, Abraham Cano Aguilera, X. Arnal I Clemente, M. P. Podles, José Luis Imaña, Idelfonso Tafur Monroy, J. J. Vegas Olmos
2024 — conf
First Line-rate End-to-End Post-Quantum Encrypted Optical Fiber Link Using Data Processing Units (DPUs).
OFC
Abraham Cano Aguilera, Rana Abu Bakar, Faris Alhamed, Carlos Rubio Garcia, José Luis Imaña, Idelfonso Tafur Monroy, Filippo Cugini, J. J. Vegas Olmos
2024 B conf
Integrating Post-Quantum Cryptography Plugins for IPsec Offloads to Data Processing Units in the Cloud-Edge Continuum.
ICNP
Abraham Cano Aguilera, Carlos Rubio Garcia, Raphaël Frantz, Idelfonso Tafur Monroy, José Luis Imaña, Juan José Vegas Olmos
2024 J jnl
Low-Complexity Hardware Architecture of APN Permutations Using TU-Decomposition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Lilya Budaghyan, José Luis Imaña, Nikolay S. Kaleyski
2024 — conf
The zero-tax data center: a use case through quantum resilient communications.
ICTON
Daniel C. Lawo, Michal Podles, Raphael Frantz, Abraham Cano Aguilera, Dimosthenis Iliadis-Apostolidis, Jerónimo Sánchez García, Sokol Kosta, Idelfonso Tafur Monroy, José Luis Imaña, J. J. Vegas Olmos
2024 J jnl
Wireless and Fiber-Based Post-Quantum-Cryptography-Secured IPsec Tunnel.
Future Internet
Daniel C. Lawo, Rana Abu Bakar, Abraham Cano Aguilera, Filippo Cugini, José Luis Imaña, Idelfonso Tafur Monroy, Juan Jose Vegas Olmos
2023 J jnl
Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks.
Inf. Process. Lett.
José Luis Imaña, Siemen Dhooghe
2023 J jnl
Hardware architecture of Dillon's APN permutation for different primitive polynomials.
Microprocess. Microsystems
José Luis Imaña, Nikolay S. Kaleyski, Lilya Budaghyan
2022 C conf
Decomposition of Dillon's APN Permutation with Efficient Hardware Implementation.
WAIFI
José Luis Imaña, Lilya Budaghyan, Nikolay S. Kaleyski
2022 J jnl
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap.
José Luis Imaña, Pengzhou He, Tianyou Bao, Yazheng Tu, Jiafeng Xie
2022 J jnl
Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Emerg. Top. Comput.
Jiafeng Xie, Pengzhou He, Xiaofang Wang, José Luis Imaña
2022 Misc conf
Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography.
CODES+ISSS
Tianyou Bao, José Luis Imaña, Pengzhou He, Jiafeng Xie
2021 J jnl
LFSR-Based Bit-Serial GF(2
IEEE Trans. Computers
José Luis Imaña
2021 J jnl
Low-Delay FPGA-Based Implementation of Finite Field Multipliers.
IEEE Trans. Circuits Syst. II Express Briefs
José Luis Imaña
2021 J jnl
Optimized reversible quantum circuits for ${\mathbb {F}}_{2^8}$ multiplication.
Quantum Inf. Process.
José Luis Imaña
2020 Misc conf
FPGA Implementation of Post-Quantum DME Cryptosystem.
FCCM
José Luis Imaña, Ignacio Luengo
2020 J jnl
High-throughput architecture for post-quantum DME cryptosystem.
Integr.
José Luis Imaña, Ignacio Luengo
2018 Misc conf
Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials.
FCCM
José Luis Imaña
2018 J jnl
Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials.
IEEE Trans. Computers
José Luis Imaña
2018 A conf
Reconfigurable implementation of GF(2
DATE
José Luis Imaña
2016 J jnl
High-Speed Polynomial Basis Multipliers Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
José Luis Imaña
2013 J jnl
Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations.
IEEE Trans. Ind. Electron.
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
2013 J jnl
Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials.
Integr.
José Luis Imaña, Román Hermida, Francisco Tirado
2012 J jnl
Efficient Polynomial Basis Multipliers for Type-II Irreducible Pentanomials.
IEEE Trans. Circuits Syst. II Express Briefs
José Luis Imaña
2011 J jnl
Low Latency GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
José Luis Imaña
2011 J jnl
Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation.
IEEE Trans. Ind. Electron.
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
2010 B conf
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation.
FPL
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
2010 J jnl
Probabilistic Verification over GF(2
Intell. Inf. Manag.
José Luis Imaña
2008 C ed.
Arithmetic of Finite Fields, 2nd International Workshop, WAIFI 2008, Siena, Italy, July 6-9, 2008, Proceedings
WAIFI
Joachim von zur Gathen, José Luis Imaña, Çetin Kaya Koç
2006 J jnl
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials.
IEEE Trans. Computers
José Luis Imaña, Juan Manuel Sánchez, Francisco Tirado
2006 J jnl
Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields
J. VLSI Signal Process.
José Luis Imaña, Juan Manuel Sánchez
2006 J jnl
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.
IEEE Trans. Very Large Scale Integr. Syst.
José Luis Imaña, Román Hermida, Francisco Tirado
2004 — conf
Reconfigurable implementation of bit-parallel multipliers over GF(2
FPT
José Luis Imaña
2003 B conf
A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2
FPL
José Luis Imaña, Juan Manuel Sánchez