José L. Núñez-Yáñez

109 papers A 2B 9C 8Journal 50Unranked 40

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Finite Word-Length Effects for Symmetric Matrix Inversion with Vector-Based Algorithms. IEEECONF Olle Hansson, José L. Núñez-Yáñez, Oscar Gustafsson
2025	J	`jnl`	SGRACE: Scalable Architecture for On-Device Inference and Training of Graph Attention and Convolutional Networks. IEEE Trans. Very Large Scale Integr. Syst. José L. Núñez-Yáñez, Hadi Mousanejad Jeddi
2025	—	`conf`	Towards Efficient Load Balancing BFS on GPUs: One Code for AMD, Intel & Nvidia. SC Workshops Kaan Olgu, Tobias Kenter, José L. Núñez-Yáñez, Simon McIntosh-Smith, Tom Deakin
2024	J	`jnl`	A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems. Inf. Habib Taha Kose, José L. Núñez-Yáñez, Robert J. Piechocki, James Pope
2024	—	`conf`	Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device Training. NorCAS José L. Núñez-Yáñez
2024	J	`jnl`	Advanced Millimeter-Wave Radar System for Real-Time Multiple-Human Tracking and Fall Detection. Sensors Zichao Shen, José L. Núñez-Yáñez, Naim Dahnoun
2024	—	`conf`	Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training. ARC Olle Hansson, Mahdieh Grailoo, Oscar Gustafsson, José L. Núñez-Yáñez
2024	—	`conf`	Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform. NorCAS Mahdieh Grailoo, Tooraj Nikoubin, José L. Núñez-Yáñez
2024	—	`conf`	Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks. NorCAS Olle Hansson, Oscar Gustafsson, José L. Núñez-Yáñez
2024	—	`conf`	Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks. NorCAS Hadi Mousanejad Jeddi, Mahdieh Grailoo, José L. Núñez-Yáñez
2024	—	`conf`	MMIDNet: Secure Human Identification Using Millimeter-wave Radar and Deep Learning. MECO Zichao Shen, José L. Núñez-Yáñez, Naim Dahnoun
2024	—	`conf`	Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures. IWOCL Kaan Olgu, Tobias Kenter, José L. Núñez-Yáñez, Simon McIntosh-Smith
2023	—	`conf`	Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows. ARC José L. Núñez-Yáñez
2023	J	`jnl`	Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis. CoRR Kris Nikov, Kyriakos Georgiou, Zbigniew Chamski, Kerstin Eder, José L. Núñez-Yáñez
2023	J	`jnl`	Big-Little Adaptive Neural Networks on Low-Power Near-Subthreshold Processors. CoRR Zichao Shen, Neil J. Howard, José L. Núñez-Yáñez
2023	J	`jnl`	Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite. CoRR José L. Núñez-Yáñez, Andrés Otero, Eduardo de la Torre
2023	J	`jnl`	Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. Microprocess. Microsystems José L. Núñez-Yáñez, J. Andrés Otero, Eduardo de la Torre
2023	—	`conf`	EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications. WCET Simon Wegener, Kris K. Nikov, José L. Núñez-Yáñez, Kerstin Eder
2023	J	`jnl`	EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications. CoRR Simon Wegener, Kris K. Nikov, José L. Núñez-Yáñez, Kerstin Eder
2023	—	`conf`	Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. ARC Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez
2023	—	`conf`	Multiple Human Tracking and Fall Detection Real-Time System Using Millimeter-Wave Radar and Data Fusion. MECO Zichao Shen, José L. Núñez-Yáñez, Naim Dahnoun
2022	C	`conf`	A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher. DSD Zijie Wang, Jiajun Lu, José L. Núñez-Yáñez
2022	—	`conf`	Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis. ICECS 2022 Kris Nikov, Kyriakos Georgiou, Zbigniew Chamski, Kerstin Eder, José L. Núñez-Yáñez
2022	C	`conf`	Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications. DSD Kaan Olgu, Kris Nikov, José L. Núñez-Yáñez
2022	J	`jnl`	Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite. IEEE Micro José L. Núñez-Yáñez
2022	J	`jnl`	Lightweight asynchronous scheduling in heterogeneous reconfigurable systems. J. Syst. Archit. Andrés Rodríguez, Angeles G. Navarro, Kris Nikov, José L. Núñez-Yáñez, Ruben Gran, Darío Suárez Gracia, Rafael Asenjo
2022	J	`jnl`	Robust and Accurate Fine-Grain Power Models for Embedded Systems With No On-Chip PMU. IEEE Embed. Syst. Lett. Kris Nikov, Marcos Martínez, Simon Wegener, José L. Núñez-Yáñez, Zbigniew Chamski, Kyriakos Georgiou, Kerstin Eder
2021	J	`jnl`	Energy-efficient neural networks with near-threshold processors and hardware accelerators. J. Syst. Archit. José L. Núñez-Yáñez, Neil J. Howard
2021	J	`jnl`	Robust and accurate fine-grain power models for embedded systems with no on-chip PMU. CoRR Kris Nikov, Marcos Martínez, Simon Wegener, José L. Núñez-Yáñez, Zbigniew Chamski, Kyriakos Georgiou, Kerstin Eder
2021	J	`jnl`	Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks. Array José L. Núñez-Yáñez, Mohammad Hosseinabady
2020	J	`jnl`	Evaluation of hybrid run-time power models for the ARM big.LITTLE architecture. CoRR Kris Nikov, José L. Núñez-Yáñez, Matthew Horsnell
2020	J	`jnl`	High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip. CoRR Kris Nikov, Mohammad Hosseinabady, Rafael Asenjo, Andrés Rodríguez, Angeles G. Navarro, José L. Núñez-Yáñez
2020	J	`jnl`	Intra and inter-core power modelling for single-ISA heterogeneous processors. Int. J. Embed. Syst. Krastin Nikov, José L. Núñez-Yáñez
2020	J	`jnl`	Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. J. Supercomput. Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran, Darío Suárez Gracia, José L. Núñez-Yáñez
2020	J	`jnl`	Performance and Energy Trade-Offs for Parallel Applications on Heterogeneous Multi-Processing Systems. CoRR Demetrios A. M. Coutinho, Daniele De Sensi, Arthur Francisco Lorenzon, Kyriakos Georgiou, José L. Núñez-Yáñez, Kerstin Eder, Samuel Xavier de Souza
2020	J	`jnl`	Remaining Useful Life Estimation Using Long Short-Term Memory Neural Networks and Deep Fusion. IEEE Access Yang Zhang, Paul Hutchinson, Nicholas A. J. Lieven, José L. Núñez-Yáñez
2020	—	`conf`	Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. PARMA-DITAM@HiPEAC José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady
2020	J	`jnl`	Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. CoRR José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady
2020	—	`conf`	Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System. PARMA-DITAM@HiPEAC Mohammad Hosseinabady, José L. Núñez-Yáñez
2019	J	`jnl`	Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
2019	—	`conf`	Energy Proportional Heterogenous Computing with Reconfigurable MPSoC. HPCS José L. Núñez-Yáñez
2019	J	`jnl`	Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling. IEEE Trans. Computers José L. Núñez-Yáñez
2019	J	`jnl`	Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs. J. Syst. Archit. Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran Tejero, Darío Suárez Gracia, José L. Núñez-Yáñez
2019	J	`jnl`	Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities. CoRR Mohammad Hosseinabady, Mohd Amiruddin Bin Zainol, José L. Núñez-Yáñez
2019	J	`jnl`	High-Performance Ultrasonic Levitation with FPGA-based Phased Arrays. CoRR William Beasley, Brenda Gatusch, Daniel Connolly-Taylor, Chenyuan Teng, Asier Marzo, José L. Núñez-Yáñez
2019	C	`conf`	Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications. VLSI-SoC Demetrios A. M. Coutinho, Kyriakos Georgiou, Kerstin I. Eder, José L. Núñez-Yáñez, Samuel Xavier-de-Souza
2019	J	`jnl`	Relationship Detection Measures for Binary SoC Data. CoRR Dave McEwan, José L. Núñez-Yáñez
2019	—	`conf`	Relationship Estimation Metrics for Binary SoC Data. LOD Dave McEwan, José L. Núñez-Yáñez
2019	J	`jnl`	Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran
2019	—	`conf`	Ultrasonic Levitation with Software-Defined FPGAs and Electronically Phased Arrays. AHS William Beasley, Brenda Gatusch, Daniel Connolly-Taylor, Chenyuan Teng, Asier Marzo, José L. Núñez-Yáñez
2019	—	`conf`	Visualizations for Understanding SoC Behaviour. PRIME Dave McEwan, Marcin Hlond, José L. Núñez-Yáñez
2018	A	`conf`	Multi-precision convolutional neural networks on heterogeneous hardware. DATE Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José L. Núñez-Yáñez
2018	J	`jnl`	Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. CoRR José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
2018	J	`jnl`	Reconfigurable Network Stream Processing on Virtualized FPGA Resources. Int. J. Reconfigurable Comput. Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas
2018	B	`conf`	Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. FPL Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, José L. Núñez-Yáñez
2017	J	`jnl`	Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors. Microprocess. Microsystems José L. Núñez-Yáñez
2017	J	`jnl`	Energy proportional streaming spiking neural network in a reconfigurable system. Microprocess. Microsystems Felipe Galindo Sanchez, José L. Núñez-Yáñez
2017	—	`conf`	Optimal compression of vibration data with lifting wavelet transform and context-based arithmetic coding. EUSIPCO Yang Zhang, Paul Hutchinson, Nicholas A. J. Lieven, José L. Núñez-Yáñez
2017	—	`conf`	Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. PARCO José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
2017	—	`conf`	Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. ReConFig Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas
2016	—	`conf`	Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application. ARC José L. Núñez-Yáñez
2016	J	`jnl`	Editorial to special issue on energy efficient architectures for embedded systems. EURASIP J. Embed. Syst. Nuno Roma, José L. Núñez-Yáñez
2016	J	`jnl`	Energy Efficient Video Fusion with Heterogeneous CPU-FPGA Devices. CoRR José L. Núñez-Yáñez, Tom Sun
2016	A	`conf`	Energy efficient video fusion with heterogeneous CPU-FPGA devices. DATE Peng Sun, Alin Achim, Ian Hasler, Paul R. Hill, José L. Núñez-Yáñez
2015	C	`conf`	Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture. EUC Krastin Nikov, José L. Núñez-Yáñez, Matthew Horsnell
2015	J	`jnl`	Guest Editorial. IET Comput. Digit. Tech. José L. Núñez-Yáñez, J. M. Moreno, Dimitrios S. Nikolopoulos
2015	—	`conf`	Workload distribution and balancing in FPGAs and CPUs with OpenCL and TBB. PARCO Rafael Asenjo, Angeles G. Navarro, Andrés Rodríguez, José L. Núñez-Yáñez
2014	B	`conf`	Accurate power control and monitoring in ZYNQ boards. FPL Arash Farhadi Beldachi, José L. Núñez-Yáñez
2014	J	`jnl`	Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling. SIGARCH Comput. Archit. News José L. Núñez-Yáñez
2014	B	`conf`	Joint video fusion and super resolution based on Markov random fields. ICIP Jin Chen, José L. Núñez-Yáñez, Alin Achim
2014	—	`conf`	Optimizing Memory Power in Hybrid ARM-FPGA Chips With Lossless Data Compression. FPGAworld Peng Sun, José L. Núñez-Yáñez
2014	—	`conf`	Power modelling and capping for heterogeneous ARM/FPGA SoCs. FPT Yun Wu, José L. Núñez-Yáñez, Roger F. Woods, Dimitrios S. Nikolopoulos
2014	J	`jnl`	Run-time power and performance scaling in 28 nm FPGAs. IET Comput. Digit. Tech. Arash Beldachi, José L. Núñez-Yáñez
2014	—	`conf`	Run-time power and performance scaling with CPU-FPGA hybrids. AHS José L. Núñez-Yáñez, Arash Beldachi
2014	J	`jnl`	eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip. IET Comput. Digit. Tech. Arash Beldachi, Simon J. Hollis, José L. Núñez-Yáñez
2013	J	`jnl`	Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip. Microprocess. Microsystems José L. Núñez-Yáñez, Geza Lore
2013	—	`conf`	Energy proportional computing in commercial FPGAs with adaptive voltage scaling. FPGAworld José L. Núñez-Yáñez
2013	B	`conf`	Video super-resolution using low rank matrix completion. ICIP Jin Chen, José L. Núñez-Yáñez, Alin Achim
2012	—	`conf`	Approximate alpha-stable Markov Random Fields for video super-resolution. EUSIPCO Jin Chen, José L. Núñez-Yáñez, Alin Achim
2012	—	`conf`	Exploring dynamically reconfigurable multicore designs with NoRC designer. HPCS José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady
2012	J	`jnl`	Video Super-Resolution Using Generalized Gaussian Markov Random Fields. IEEE Signal Process. Lett. Jin Chen, José L. Núñez-Yáñez, Alin Achim
2011	J	`jnl`	Multi-standard reconfigurable motion estimation processor for hybrid video codecs. IET Comput. Digit. Tech. José L. Núñez-Yáñez, Trevor Spiteri, George Vafiadis
2010	B	`conf`	Dynamic Reconfiguration Optimisation with Streaming Data Decompression. FPL Atukem Nabina, José L. Núñez-Yáñez
2010	C	`conf`	Effective modelling of large NoCs using SystemC. ISCAS Mohammad Hosseinabady, José L. Núñez-Yáñez
2010	C	`conf`	SystemC Architectural Transaction Level Modelling for Large NoCs. FDL Mohammad Hosseinabady, José L. Núñez-Yáñez
2009	B	`conf`	A biophysically accurate floating point somatic neuroprocessor. FPL Yiwei Zhang, José L. Núñez-Yáñez, Joe McGeehan, Edward Regan, Stephen Kelly
2009	J	`jnl`	Backward Adaptive Pixel-based Fast Predictive Motion Estimation. IEEE Signal Process. Lett. Xiaolin Chen, Nishan Canagarajah, José L. Núñez-Yáñez
2009	—	`conf`	Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. CCA/ISIC José L. Núñez-Yáñez, Mohammad Hosseinabady, Atukem Nabina, Izhar Zaidi
2009	B	`conf`	Run-time resource management in fault-tolerant network on reconfigurable chips. FPL Mohammad Hosseinabady, José L. Núñez-Yáñez
2008	J	`jnl`	A Novel Delta Sigma Control System Processor and Its VLSI Implementation. IEEE Trans. Very Large Scale Integr. Syst. Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall
2008	J	`jnl`	Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. IET Comput. Digit. Tech. José L. Núñez-Yáñez, Doug A. Edwards, Antonio Marcello Coppola
2008	J	`jnl`	Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study. Integr. Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, Dionysios I. Reisis, Konstantinos Nakos, Konstantinos Manolopoulos
2008	B	`conf`	Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. FPL Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez
2008	—	`conf`	Fault-tolerant dynamically reconfigurable NoC-based SoC. ASAP Mohammad Hosseinabady, José L. Núñez-Yáñez
2008	—	`conf`	Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. ARC Xiaolin Chen, Cedric Nishan Canagarajah, Raffaele Vitulli, José L. Núñez-Yáñez
2008	C	`conf`	Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. DSD Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez
2007	B	`conf`	Dynamic Voltage Scaling in a FPGA-based System-on-Chip. FPL José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler
2007	C	`conf`	On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS R. Stapenhurst, Koushik Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan
2006	—	`conf`	A Novel Processor Architecture for Real-Time Control. Asia-Pacific Computer Systems Architecture Conference Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova
2006	J	`jnl`	Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec. IEEE Trans. Consumer Electron. José L. Núñez-Yáñez, Vassilios A. Chouliaras, Daniele Alfonso, Fabrizio S. Rovati
2005	J	`jnl`	A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding. IEEE Trans. Computers José L. Núñez-Yáñez, Vassilios A. Chouliaras
2005	—	`conf`	A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor. ASAP Tom R. Jacobs, José L. Núñez-Yáñez
2005	J	`jnl`	A multi-standard video accelerator based on a vector architecture. IEEE Trans. Consumer Electron. Vassilios A. Chouliaras, José L. Núñez-Yáñez, David J. Mulvaney, Fabrizio S. Rovati, Daniele Alfonso
2005	—	`conf`	Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards. SIP Konstantia Koutsomyti, S. R. Parr, Vassilios A. Chouliaras, José L. Núñez-Yáñez
2005	—	`conf`	Configurable Multiprocessors for High-Performance MPEG-4 Video Coding. ISVLSI Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez
2005	—	`conf`	Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec. ASAP José L. Núñez-Yáñez, Vassilios A. Chouliaras
2005	J	`jnl`	High-performance arithmetic coding VLSI macro for the H264 video compression standard. IEEE Trans. Consumer Electron. José L. Núñez-Yáñez, Vassilios A. Chouliaras
2003	—	`conf`	A code compression scheme for improving SoC performance. SoC E. G. Nikolova, David J. Mulvaney, Vassilios A. Chouliaras, José L. Núñez-Yáñez
2003	J	`jnl`	Scalar coprocessors for accelerating the G723.1 and G729A speech coders. IEEE Trans. Consumer Electron. Vassilios A. Chouliaras, José L. Núñez-Yáñez