José G. Delgado-Frias

107 papers A 3B 7C 10Misc 1Journal 34Unranked 51

Year	Rank	Type	Title / Venue / Authors
2022	C	`conf`	ACHS Optimizations on 3D Interconnect Arrangements. ISCAS Daniel Iparraguirre, José G. Delgado-Frias
2022	J	`jnl`	Asymmetric Crosstalk Harness Signaling for Common Eigenmode Elimination. IEEE Trans. Computers Daniel Iparraguirre, José G. Delgado-Frias, Howard Heck
2022	J	`jnl`	Asymmetric Crosstalk Harnessed Signaling for Large 3D Routing Integration. IEEE Trans. Circuits Syst. II Express Briefs Daniel Iparraguirre, José G. Delgado-Frias
2021	C	`conf`	A Crosstalk-Harnessed Signaling Enhancement that Eliminates Common-Mode Encoding. ISCAS Daniel Iparraguirre, José G. Delgado-Frias, Howard Heck
2020	J	`jnl`	Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating. IEEE Trans. Circuits Syst. II Express Briefs Michael A. Turi, José G. Delgado-Frias
2020	J	`jnl`	MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. José Silva-Martínez, José G. Delgado-Frias
2020	J	`jnl`	Online Firmware Functional Validation Scheme Using Colored Petri Net Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Yi Qian, Rahul Khanna
2017	—	`conf`	An implemented, initialization algorithm for many-dimension, Monte Carlo circuit simulations using Spice. CCWC Michael A. Turi, José G. Delgado-Frias
2017	—	`conf`	Firmware functional validation using a Colored Petri Net model. MWSCAS Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Rahul Khanna
2017	J	`jnl`	Full-V Integr. Michael A. Turi, José G. Delgado-Frias
2016	—	`conf`	A real-time UEFI functional validation tool with behavior Colored Petri Net model. MWSCAS Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Rahul Khanna
2016	J	`jnl`	Autonomous management of a recursive area hierarchy for large scale wireless sensor networks using multiple parents. Ad Hoc Networks Johnathan Vee Cree, José G. Delgado-Frias
2015	C	`conf`	Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance. ISCAS José G. Delgado-Frias, Zhe Zhang, Michael A. Turi
2015	—	`conf`	UEFI USB bus initialization verification using Colored Petri Net. MWSCAS Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Rahul Khanna
2014	—	`conf`	An evaluation of 6T and 8T FinFET SRAM cell leakage currents. MWSCAS Michael A. Turi, José G. Delgado-Frias
2014	—	`conf`	Welcome to MWSCAS 2014. MWSCAS José Silva-Martínez, Edgar Sánchez-Sinencio, José G. Delgado-Frias, Randall L. Geiger
2013	C	`conf`	CNTFET 8T SRAM cell performance with near-threshold power supply scaling. ISCAS Zhe Zhang, José G. Delgado-Frias
2013	—	`conf`	Management of large-scale wireless sensor networks utilizing multi-parent recursive area hierarchies. IGCC Johnathan Vee Cree, José G. Delgado-Frias
2013	—	`conf`	Near-threshold CNTFET SRAM cell design with gated cell power supply. MWSCAS Zhe Zhang, José G. Delgado-Frias
2012	—	`conf`	A superscalar processor for a medium-grain reconfigurable hardware. MWSCAS Jason Van Dyken, José G. Delgado-Frias
2012	—	`conf`	CNTFET SRAM cell with tolerance to removed metallic CNTs. MWSCAS Zhe Zhang, José G. Delgado-Frias
2012	—	`conf`	FinFET 3T and 3T1D dynamic RAM cells. MWSCAS Colby M. Gerik, Michael A. Turi, José G. Delgado-Frias
2012	—	`conf`	NOA: A Scalable Multi-Parent Clustering Hierarchy for WSNs. ANT/MobiWIS Johnathan Vee Cree, José G. Delgado-Frias, Mike Hughes, Brion Burghard, Kurt Silvers
2012	—	`conf`	SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells. ACM Great Lakes Symposium on VLSI Zhe Zhang, Michael A. Turi, José G. Delgado-Frias
2010	—	`conf`	FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters. ReConFig G. Ramirez-Conejo, Javier Díaz-Carmona, Agustín Ramírez-Agundis, Alfredo Padilla-Medina, José G. Delgado-Frias
2010	J	`jnl`	FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm. J. Syst. Archit. Jason Van Dyken, José G. Delgado-Frias
2010	—	`conf`	Low power SRAM cell design for FinFET and CNTFET technologies. Green Computing Conference José G. Delgado-Frias, Zhe Zhang, Michael A. Turi
2009	J	`jnl`	Decreasing energy consumption in address decoders by means of selective precharge schemes. Microelectron. J. Michael A. Turi, José G. Delgado-Frias
2009	—	`conf`	Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures. ERSA Kylan Robinson, José G. Delgado-Frias
2009	J	`jnl`	IP Routing table compaction and sampling schemes to enhance TCAM cache performance. J. Syst. Archit. Ruirui Guo, José G. Delgado-Frias
2008	J	`jnl`	A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. IEEE Trans. Very Large Scale Integr. Syst. Mitchell J. Myjak, José G. Delgado-Frias
2008	—	`conf`	FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. ERSA Jason Van Dyken, José G. Delgado-Frias, Sirisha Medidi
2008	J	`jnl`	High-Performance Low-Power Selective Precharge Schemes for Address Decoders. IEEE Trans. Circuits Syst. II Express Briefs Michael A. Turi, José G. Delgado-Frias
2008	C	`conf`	High-performance low-power AND and Sense-Amp address decoders with selective precharging. ISCAS Michael A. Turi, José G. Delgado-Frias
2008	J	`jnl`	Intelligent management of distributed dynamic sensor networks. Artif. Life Robotics Peter Sapaty, Masanori Sugisaka, José G. Delgado-Frias, Joaquim Filipe, Nikolay N. Mirenkov
2008	J	`jnl`	Performance analysis of multipath transmission over 802.11-based multihop ad hoc networks: a cross-layer perspective. IET Commun. Li Zhao, José G. Delgado-Frias, Krishnamoorthy Sivakumar
2007	—	`conf`	A novel compaction scheme for routing tables in TCAM to enhance cache hit rate. Communications, Internet, and Information Technology R. Guo, José G. Delgado-Frias
2007	J	`jnl`	Emergent societies: advanced IT support of crisis relief missions. Artif. Life Robotics Peter Sapaty, Masanori Sugisaka, Robert Finkelstein, José G. Delgado-Frias, Nikolay N. Mirenkov
2007	J	`jnl`	Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers. IEEE Trans. Parallel Distributed Syst. Rongsen He, José G. Delgado-Frias
2007	C	`conf`	Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. ISCAS Daniel R. Blum, José G. Delgado-Frias
2007	B	`conf`	MARS: Misbehavior Detection in Ad Hoc Networks. GLOBECOM Li Zhao, José G. Delgado-Frias
2007	J	`jnl`	Medium-Grain Cells for Reconfigurable DSP Hardware. IEEE Trans. Circuits Syst. I Regul. Pap. Mitchell J. Myjak, José G. Delgado-Frias
2007	J	`jnl`	Preface. Integr. Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru
2007	B	`conf`	Redundant Array of Independent Fabrics - An Architecture for Next Generation Network. GLOBECOM Rongsen He, José G. Delgado-Frias
2007	—	`conf`	Using a Cache Scheme to Detect Misbehaving Nodes in Mobile Ad-Hoc Networks. ICON Hongxun Liu, José G. Delgado-Frias, Sirisha Medidi
2007	—	`conf`	Using a cache scheme to detect selfish nodes in mobile ad hoc networks. Communications, Internet, and Information Technology H. Lin, José G. Delgado-Frias, Sirisha Medidi
2007	—	`conf`	Using a two-timer scheme to detect selfish nodes in mobile ad-hoc networks. Communications, Internet, and Information Technology H. Lui, José G. Delgado-Frias, Sirisha Medidi
2006	C	`conf`	A mesochronous pipeline scheme for high performance low power digital systems. ISCAS Suryanarayana Tatapudi, José G. Delgado-Frias
2006	J	`jnl`	A mesochronous pipelining scheme for high-performance digital systems. IEEE Trans. Circuits Syst. I Regul. Pap. Suryanarayana Tatapudi, José G. Delgado-Frias
2006	B	`conf`	Interleaved Multistage Switching Fabrics for Scalable High Performance Routers. GLOBECOM Rongsen He, José G. Delgado-Frias
2006	—	`conf`	Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture. ERSA Mitchell J. Myjak, Jonathan Larson, José G. Delgado-Frias
2006	B	`conf`	Multipath Routing Based Secure Data Transmission in Ad Hoc Networks. WiMob Li Zhao, José G. Delgado-Frias
2006	—	`conf`	On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks. Wireless and Optical Communications Li Zhao, José G. Delgado-Frias
2006	B	`conf`	Performance Analysis of Multipath Data Transmission in Multihop Ad Hoc Networks. SECON Li Zhao, José G. Delgado-Frias
2006	C	`conf`	Superpipelined reconfigurable hardware for DSP. ISCAS Mitchell J. Myjak, José G. Delgado-Frias
2005	—	`conf`	A High Performance Hybrid Wave-Pipelined Multiplier. ISVLSI Suryanarayana Tatapudi, José G. Delgado-Frias
2005	—	`conf`	A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. CDES Suryanarayana Tatapudi, José G. Delgado-Frias
2005	—	`conf`	A Symmetric Differential Clock Generator for Bit-Serial Hardware. CDES Mitchell J. Myjak, José G. Delgado-Frias
2005	—	`conf`	A distributed FIFO scheme for on chip communication. ISCAS (2) Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
2005	—	`conf`	DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. CDES Jin Liu, José G. Delgado-Frias
2005	J	`jnl`	Decoupled dynamic ternary content addressable memories. IEEE Trans. Circuits Syst. I Regul. Pap. José G. Delgado-Frias, Jabulani Nyathi, Suryanarayana Tatapudi
2005	—	`conf`	Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. CDES Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias
2005	—	`ed.`	Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005 CDES Laurence Tianruo Yang, Hamid R. Arabnia, Yiming Li, Salam N. Salloum, José G. Delgado-Frias
2004	—	`conf`	A Distributed FIFO Scheme for System on Chip Inter-Component Communication. ESA/VLSI Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
2004	—	`conf`	An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware. ESA/VLSI Andy Widjaja, José G. Delgado-Frias
2004	—	`conf`	H-Tree Interconnection Structure for Reconfigurable DSP Hardware. ERSA Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias
2004	A	`conf`	Pipelined Multipliers for Reconfigurable Hardware. IPDPS Mitchell J. Myjak, José G. Delgado-Frias
2003	—	`conf`	A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. VLSI Daniel R. Blum, José G. Delgado-Frias
2003	—	`conf`	A Reconfigurable Switch for a DSP Array. VLSI Fred L. Anderson IV, José G. Delgado-Frias
2003	—	`conf`	A Two-Level Reconfigurable Architecture for Digital Signal Processing. VLSI Mitchell J. Myjak, José G. Delgado-Frias
2001	—	`conf`	A VLSI wrapped wave front arbiter for crossbar switches. ACM Great Lakes Symposium on VLSI José G. Delgado-Frias, Girish B. Ratanpal
2001	—	`conf`	BASIS: A Biological Approach to System Information Security. MMM-ACNS Victor A. Skormin, José G. Delgado-Frias, Dennis L. McGee, Joseph Giordano, Leonard J. Popyack, Vladimir I. Gorodetski, Alexander O. Tarakanov
2000	C	`conf`	A wave-pipelined CMOS associate router for communication switches. ISCAS José G. Delgado-Frias, Jabulani Nyathi
2000	—	`conf`	A wave-pipelined router architecture using ternary associative memory. ACM Great Lakes Symposium on VLSI José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan
2000	J	`jnl`	Elementary function generators for neural-network emulators. IEEE Trans. Neural Networks Learn. Syst. Stamatis Vassiliadis, Ming Zhang, José G. Delgado-Frias
1999	J	`jnl`	A neuro-emulator with embedded capabilities for generalized learning. J. Syst. Archit. Valentine C. Aikens II, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis
1998	J	`jnl`	A Clustering and Genetic Scheme for Large Tsp Optimization Problems. Cybern. Syst. Chien-Ying Lu, José G. Delgado-Frias, Wei Lin
1998	—	`conf`	A Dictionary Machine Emulation on a VLSI Computing Tree System. Great Lakes Symposium on VLSI Adger E. Harvin III, José G. Delgado-Frias
1998	—	`conf`	A VLSI High-Performance Encoder with Priority Lookahead. Great Lakes Symposium on VLSI José G. Delgado-Frias, Jabulani Nyathi
1998	—	`conf`	A VLSI Self-Compacting Buffer for DAMQ Communication Switches. Great Lakes Symposium on VLSI José G. Delgado-Frias, Richard Diaz
1998	Misc	`conf`	Approaches for determining dynamic synchronization resource requirements. CATA Douglas H. Summerville, José G. Delgado-Frias
1998	J	`jnl`	Executing tree routing algorithms on a high-performance pattern associative router. J. Syst. Archit. Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis
1996	J	`jnl`	A Flexible Bit-Pattern Associative Router for Interconnection Networks. IEEE Trans. Parallel Distributed Syst. Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis
1996	—	`conf`	A Pattern-Associative Router for Interconnection Network Adaptive Algorithms. Euro-Par, Vol. I Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville
1996	—	`conf`	A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. Great Lakes Symposium on VLSI José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville
1996	—	`conf`	A neuro-emulator with learning and virtual emulation capabilities. ICNN Valentine C. Aikens II, José G. Delgado-Frias, Steven M. Barber, Gerald G. Pechanek, Stamatis Vassiliadis
1996	J	`jnl`	Sigmoid Generators for Neural Computing Using Piecewise Approximations. IEEE Trans. Computers Ming Zhang, Stamatis Vassiliadis, José G. Delgado-Frias
1996	J	`jnl`	Software Metrics and Microcode: A Case Study. J. Softw. Maintenance Res. Pract. George Triantafyllos, Stamatis Vassiliadis, José G. Delgado-Frias
1995	—	`conf`	A Neuro-Architecture with Embedded Learning. Parallel and Distributed Computing and Systems Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis
1995	—	`conf`	A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks. Parallel and Distributed Computing and Systems Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville
1995	—	`conf`	A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing. Parallel and Distributed Computing and Systems Adger E. Harvin III, José G. Delgado-Frias
1995	J	`jnl`	Flexible oblivious router architecture. IBM J. Res. Dev. Joonho Park, Stamatis Vassiliadis, José G. Delgado-Frias
1995	J	`jnl`	The multi-associative branch target buffer: a cost effective BTB mechanism. Microprocess. Microprogramming Weili Chu, Stamatis Vassiliadis, José G. Delgado-Frias
1994	—	`conf`	A High Performance Pattern Associative Oblivious Router for Tree Topologies. IPPS Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis
1994	—	`conf`	A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks. Great Lakes Symposium on VLSI José G. Delgado-Frias, Rovy Sze, Douglas H. Summerville, Valentine C. Aikens II
1994	J	`jnl`	An investigation of binary CLA and ripple CMOS adder designs. Microprocess. Microprogramming Chuan-Jen Chang, Stamatis Vassiliadis, José G. Delgado-Frias
1994	A	`conf`	Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers. SC Joonho Park, Brian W. O'Krafka, Stamatis Vassiliadis, José G. Delgado-Frias
1993	—	`conf`	A massively parallel diagonal-fold array processor. ASAP Gerald G. Pechanek, José G. Delgado-Frias, Stamatis Vassiliadis
1993	J	`jnl`	Spin: the Sequential Pipelined Neuroemulator. Int. J. Artif. Intell. Tools Stamatis Vassiliadis, Gerald G. Pechanek, José G. Delgado-Frias
1992	J	`jnl`	Digital neural emulators using tree accumulation and communication structures. IEEE Trans. Neural Networks Gerald G. Pechanek, Stamatis Vassiliadis, José G. Delgado-Frias
1992	J	`jnl`	Semantic Network Architectures: an Evaluation. Int. J. Artif. Intell. Tools José G. Delgado-Frias, Stamatis Vassiliadis, Jamshid Goshtasbi
1991	B	`conf`	AI in multimedia (panel session). ICTAI Nikolaos G. Bourbakis, Robin Williams, Forouzan Golshani, Myron Flickner, Ted Laliotis, Sukhan Lee, José G. Delgado-Frias, Dan Hammerstrom, Cris Koutsougeras, Gerald G. Pechanek, Benjamin W. Wah, John Yen, Farokh B. Bastani, Tom Cooper, Karan Harbison-Briggs, Rudy Lauber, Alun D. Preece, Imran A. Zualkernan, W. T. Tsai, Daniel E. Cooke, Martin S. Feather, Stephen Fickas, N. Minsky, Peter G. Selfridge, Douglas Smith
1991	C	`conf`	MPU: A N-Tuple Matching Processor. ICCD Robert H. Payne, José G. Delgado-Frias
1991	B	`conf`	SPIN: a sequential pipelined neurocomputer. ICTAI Stamatis Vassiliadis, Gerald G. Pechanek, José G. Delgado-Frias
1989	—	`conf`	A semantic network architecture for artificial intelligence processing. TAI José G. Delgado-Frias, Will R. Moore
1988	A	`conf`	BVE: a wafer-scale engine for differential equation computation. ICS José G. Delgado-Frias, D. M. Green
1988	J	`jnl`	Parallel architectures for AI semantic network processing. Knowl. Based Syst. José G. Delgado-Frias, Will R. Moore