José Flich - RankMe

193 papers A* 3A 23B 18C 14Misc 7Journal 56Unranked 65

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Peformance Isolation for Inference Processes in Edge GPU Systems. CoRR Juan José Martín, José Flich, Carles Hernández
2025	J	`jnl`	Exploiting neural networks bit-level redundancy to mitigate the impact of faults at inference. J. Supercomput. Izan Catalán, José Flich, Carles Hernández
2025	J	`jnl`	SIRENA: SparsIty-REpetition aware Nibble-based hardware Accelerator for convolutional neural networks. J. Syst. Archit. Laura Medina, José Flich
2025	—	`conf`	Scalable Neural Network Training: Distributed Data-Parallel Approaches. SC Workshops Fernando Vázquez-Novoa, Pedro López, José Flich, Rosa M. Badia
2023	—	`conf`	An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture Exploration. DCIS Rafael Tornero, David Rodriguez, José Maria Martínez, José Flich
2023	—	`conf`	GEMM-Like Convolution for Deep Learning Inference on the Xilinx Versal. ISC Workshops Jie Lei, Héctor Martínez, José Flich, Enrique S. Quintana-Ortí
2023	A	`conf`	NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. DATE Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov
2023	—	`conf`	On the Potentials of Input Repetition in CNN Networks for Reducing Multiplications. PKDD/ECML Workshops (4) Laura Medina, José Flich
2023	C	`conf`	Toward Matrix Multiplication for Deep Learning Inference on the Xilinx Versal. PDP Jie Lei, José Flich, Enrique S. Quintana-Ortí
2023	J	`jnl`	Toward matrix multiplication for deep learning inference on the Xilinx Versal. CoRR Jie Lei, José Flich, Enrique S. Quintana-Ortí
2023	A	`conf`	Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms. DATE David Rodriguez, Rafael Tornero, José Flich
2022	B	`conf`	Efficient Inference Of Image-Based Neural Network Models In Reconfigurable Systems With Pruning And Quantization. ICIP José Flich, Laura Medina, Izan Catalán, Carles Hernández, Andrea Bragagnolo, Fabrice Auzanneau, David Briand
2022	J	`jnl`	Enabling Dynamic and Intelligent Workflows for HPC, Data Analytics, and AI Convergence. CoRR Jorge Ejarque, Rosa M. Badia, Loïc Albertin, Giovanni Aloisio, Enrico Baglione, Yolanda Becerra, Stefan Boschert, Julian R. Berlin, Alessandro D'Anca, Donatello Elia, François Exertier, Sandro Fiore, José Flich, Arnau Folch, Steven J. Gibbons, Nikolay Koldunov, Francesc Lordan, Stefano Lorito, Finn Løvholt, Jorge Macías Sánchez, Fabrizio Marozzo, Alberto Michelini, Marisol Monterrubio Velasco, Marta Pienkowska, Josep de la Puente, Anna Queralt, Enrique S. Quintana-Ortí, Juan Esteban Rodriguez, Fabrizio Romano, Riccardo Rossi, Jedrzej Rybicki, Miroslaw Kupczyk, Jacopo Selva, Domenico Talia, Roberto Tonini, Paolo Trunfio, Manuela Volpe
2022	J	`jnl`	Enabling dynamic and intelligent workflows for HPC, data analytics, and AI convergence. Future Gener. Comput. Syst. Jorge Ejarque, Rosa M. Badia, Loïc Albertin, Giovanni Aloisio, Enrico Baglione, Yolanda Becerra, Stefan Boschert, Julian R. Berlin, Alessandro D'Anca, Donatello Elia, François Exertier, Sandro Fiore, José Flich, Arnau Folch, Steven J. Gibbons, Nikolay Koldunov, Francesc Lordan, Stefano Lorito, Finn Løvholt, Jorge Macías Sánchez, Fabrizio Marozzo, Alberto Michelini, Marisol Monterrubio Velasco, Marta Pienkowska, Josep de la Puente, Anna Queralt, Enrique S. Quintana-Ortí, Juan Esteban Rodriguez, Fabrizio Romano, Riccardo Rossi, Jedrzej Rybicki, Miroslaw Kupczyk, Jacopo Selva, Domenico Talia, Roberto Tonini, Paolo Trunfio, Manuela Volpe
2022	—	`ch.`	The DeepHealth Toolkit: A Key European Free and Open-Source Software for Deep Learning and Computer Vision Ready to Exploit Heterogeneous HPC and Cloud Architectures. Technologies and Applications for Big Data Value Marco Aldinucci, David Atienza, Federico Bolelli, Mónica Caballero, Iacopo Colonnelli, José Flich, Jon Ander Gómez, David González, Costantino Grana, Marco Grangetto, Simone Leo, Pedro López, Dana Oniga, Roberto Paredes, Luca Pireddu, Eduardo Quiñones, Tatiana Silva, Enzo Tartaglione, Marina Zapater
2022	A	`conf`	The SELENE Deep Learning Acceleration Framework for Safety-related Applications. DATE Laura Medina, Salva Carrion, Pablo Andreu, Tomás Picornell, José Flich, Carles Hernández, Michael Sandoval, Markel Sainz, Charles-Alexis Lefebvre, Martin Rönnbäck, Martin Matschnig, Matthias Wess, Herbert Taucher
2021	—	`ed.`	12th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 10th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2021, Budapest, Hungary, January 19, 2021 PARMA-DITAM@HiPEAC João Bispo, Stefano Cherubin, José Flich
2021	J	`jnl`	Enforcing Predictability of Many-Cores With DCFNoC. IEEE Trans. Computers Tomás Picornell, José Flich, Carles Hernández, José Duato
2021	A	`conf`	From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience. DATE José Flich, Rafael Tornero, David Rodriguez, Davide Russo, José Maria Martínez, Carles Hernández
2021	A	`conf`	Improving the Robustness of Redundant Execution with Register File Randomization. ICCAD Ilya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López, José Flich, Carles Hernández
2021	J	`jnl`	UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility. J. Supercomput. Juan-José Crespo, José L. Sánchez, Francisco J. Alfaro-Cortés, José Flich, José Duato
2020	—	`conf`	Distributed Training on a Highly Heterogeneous HPC System. SAMOS José Flich, Carles Hernández, Eduardo Quiñones, Roberto Paredes
2020	J	`jnl`	HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory. IEEE Access Tomás Picornell, José Flich, José Duato, Carles Hernández
2020	C	`conf`	SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems. DSD Carles Hernández, José Flich, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, Jaume Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, Jan Kiszka, Martin Rönnbäck, Johan Klockars, Nicholas Mc Guire, Franz Rammerstorfer, Christian Schwarzl, Franck Wartel, Dierk Lüdemann, Mikel Labayen
2020	J	`jnl`	TDSR: Transparent Distributed Segment-Based Routing. CoRR Juan-José Crespo, German Maglione Mathey, José L. Sánchez, Francisco J. Alfaro-Cortes, José Flich
2020	J	`jnl`	UPR: Deadlock-Free Dynamic Network Reconfiguration by Exploiting Channel Dependency Graph Compatibility. CoRR Juan-José Crespo, José L. Sánchez, Francisco J. Alfaro-Cortes, José Flich, José Duato
2019	—	`conf`	A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems. MCSoC Miguel Gorgues Alonso, José Flich, Meriem Turki, Davide Bertozzi
2019	C	`conf`	Challenges in Deeply Heterogeneous High Performance Systems. DSD Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
2019	A*	`conf`	DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip. DAC Tomás Picornell, José Flich, Carles Hernández, José Duato
2019	J	`jnl`	Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications. ACM J. Emerg. Technol. Comput. Syst. Edoardo Fusella, Mahdi Nikdast, Ian O'Connor, José Flich, Sudeep Pasricha
2018	J	`jnl`	Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni
2018	J	`jnl`	PROSA: Protocol-Driven Network on Chip Architecture. IEEE Trans. Parallel Distributed Syst. Miguel Gorgues Alonso, José Flich
2018	—	`conf`	Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farrés, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni
2017	—	`conf`	Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. PARCO José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell
2017	—	`conf`	ICARO-PAPM: Congestion Management with Selective Queue Power-Gating. HPCS José V. Escamilla, José Flich, Mario R. Casu
2017	C	`conf`	MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. DSD José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni
2017	J	`jnl`	Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby. IEEE Trans. Parallel Distributed Syst. Edoardo Fusella, José Flich, Alessandro Cilardo
2016	J	`jnl`	CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs. IEEE Trans. Parallel Distributed Syst. Davide Zoni, José Flich, William Fornaciari
2016	A	`conf`	Enabling HPC for QoS-sensitive applications: The MANGO approach. DATE José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni
2016	J	`jnl`	End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance. IEEE Comput. Archit. Lett. Miguel Gorgues, José Flich
2016	—	`conf`	Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy. MCSoC José V. Escamilla, Mario R. Casu, José Flich
2016	—	`conf`	Logic-based implementation of fault-tolerant routing in 3D network-on-chips. NOCS Behrad Niazmand, Siavoosh Payandeh Azad, José Flich, Jaan Raik, Gert Jervan, Thomas Hollstein
2015	J	`jnl`	A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106]. ACM Trans. Embed. Comput. Syst. Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich, Francisco Triviño
2015	J	`jnl`	Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Comput. Electr. Eng. Antoni Roca, Carles Hernández, Mario Lodde, José Flich
2015	—	`conf`	Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing. HPCC/CSS/ICESS Alessandro Cilardo, José Flich, Mirko Gagliardi, Rafael Tornero Gavilá
2015	—	`conf`	Efficient DVFS Operation in NoCs Through a Proper Congestion Management Strategy. Euro-Par Workshops José V. Escamilla, José Flich, Pedro Javier García
2015	J	`jnl`	Efficient and Cost-Effective Hybrid Congestion Control for HPC Interconnection Networks. IEEE Trans. Parallel Distributed Syst. Jesús Escudero-Sahuquillo, Ernst Gunnar Gran, Pedro Javier García, José Flich, Tor Skeie, Olav Lysne, Francisco J. Quiles, José Duato
2015	—	`conf`	On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs. SiPhotonics@HiPEAC Edoardo Fusella, José Flich, Alessandro Cilardo, Antonino Mazzeo
2015	—	`ed.`	Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015 NOCS André Ivanov, Diana Marculescu, Partha Pratim Pande, José Flich, Karthik Pattabiraman
2015	A	`conf`	Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration. DATE Marco Balboni, José Flich, Davide Bertozzi
2015	—	`conf`	The MANGO FET-HPC Project: An Overview. CSE José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni
2015	J	`jnl`	The fast evolving landscape of on-chip communication - Selected future challenges and research avenues. Des. Autom. Embed. Syst. Davide Bertozzi, Giorgos Dimitrakopoulos, José Flich, Sören Sonntag
2015	A	`conf`	d DATE Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich
2014	—	`conf`	Achieving balanced buffer utilization with a proper co-design of flow control and routing algorithm. NOCS Miguel Gorgues, Dong Xiang, José Flich, Zhigang Yu, José Duato
2014	J	`jnl`	Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead. IEEE Trans. Computers José Cano, José Flich, Antoni Roca, José Duato, Marcello Coppola, Riccardo Locatelli
2014	—	`conf`	ICARO: Congestion isolation in networks-on-chip. NOCS José V. Escamilla, José Flich, Pedro Javier García
2014	J	`jnl`	Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing. IEEE Trans. Computers Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, José Flich, Hannu Tenhunen
2014	—	`ed.`	Proceedings of the 8th International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC 2014, Vienna, Austria, January 22, 2014 INA-OCMC@HiPEAC Giorgos Dimitrakopoulos, Sören Sonntag, José Flich, Pascal Vivet
2014	J	`jnl`	Runtime home mapping for effective memory resource usage. Microprocess. Microsystems Mario Lodde, José Flich
2013	—	`conf`	A Lightweight Network of IDs to Quickly Deliver Simple Control Messages. Euro-Par Workshops Mario Lodde, José Flich
2013	J	`jnl`	A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich, José L. Sánchez, Francisco J. Alfaro, Michele Favalli, Davide Bertozzi
2013	—	`conf`	A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs. INA-OCMC@HiPEAC Francisco Triviño, Davide Bertozzi, José Flich
2013	—	`conf`	Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations. PATMOS Davide Zoni, José Flich, William Fornaciari
2013	J	`jnl`	An Effective and Feasible Congestion Management Technique for High-Performance MINs with Tag-Based Distributed Routing. IEEE Trans. Parallel Distributed Syst. Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato
2013	—	`conf`	An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance. NOCS Mario Lodde, José Flich
2013	J	`jnl`	Built-in fast gather control network for efficient support of coherence protocols. IET Comput. Digit. Tech. Mario Lodde, Antoni Roca, José Flich
2013	—	`conf`	CASS Introduction. IPDPS Workshops José Flich, Scott Pakin, Craig B. Stunkel
2013	—	`conf`	Head-of-Line Blocking Avoidance in Networks-on-Chip. IPDPS Workshops José V. Escamilla, José Flich, Pedro Javier García
2013	—	`conf`	Making the Network Scalable: Inter-subnet Routing in InfiniBand. Euro-Par Bartosz Bogdanski, Bjørn Dag Johnsen, Sven-Arne Reinemo, José Flich
2013	—	`conf`	Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms. ISSoC Marco Balboni, Francisco Triviño, José Flich, Davide Bertozzi
2013	—	`conf`	Power Saving by NoC Traffic Compression. Euro-Par Workshops María Soler, José Flich
2013	J	`jnl`	Silicon-aware distributed switch architecture for on-chip networks. J. Syst. Archit. Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
2013	—	`conf`	Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support. Euro-Par Mario Lodde, José Flich, Manuel E. Acacio
2012	J	`jnl`	A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms. IEEE Trans. Parallel Distributed Syst. José Flich, Tor Skeie, Andres Mejia, Olav Lysne, Pedro López, Antonio Robles, José Duato, Michihiro Koibuchi, Tomas Rokicki, José Carlos Sancho
2012	—	`conf`	CASS Introduction. IPDPS Workshops José Flich, Scott Pakin, Craig B. Stunkel
2012	B	`conf`	DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. FPL Antoni Roca, José Flich, Giorgos Dimitrakopoulos
2012	—	`conf`	Detecting Sharing Patterns in Industrial Parallel Applications for Embedded Heterogeneous Multicore Systems. Euro-Par Workshops Albert Esteve, María Soler, María Engracia Gómez, Antonio Robles, José Flich
2012	—	`conf`	Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols. Euro-Par Mario Lodde, José Flich, Manuel E. Acacio
2012	B	`conf`	Enabling High-Performance Crossbars through a Floorplan-Aware Design. ICPP Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
2012	C	`conf`	Exploring NoC Virtualization Alternatives in CMPs. PDP Francisco Triviño, José L. Sánchez, Francisco José Alfaro, José Flich
2012	—	`conf`	Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support. NOCS Mario Lodde, José Flich, Manuel E. Acacio
2012	—	`conf`	Heterogeneous network design for effective support of invalidation-based coherency protocols. INA-OCMC@HiPEAC Mario Lodde, Toni Roca, José Flich
2012	J	`jnl`	Network-on-Chip virtualization in Chip-Multiprocessor Systems. J. Syst. Archit. Francisco Triviño, José L. Sánchez, Francisco J. Alfaro, José Flich
2012	—	`conf`	OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. ICSAMOS Alessandro Strano, Davide Bertozzi, Francisco Triviño, José L. Sánchez, Francisco J. Alfaro, José Flich
2012	J	`jnl`	On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato
2012	—	`conf`	Quest for the ultimate network-on-chip: the NaNoC project. INA-OCMC@HiPEAC Alessandro Strano, Davide Bertozzi, Federico Angiolini, Leonardo Di G. Gregorio, Frank Olaf Sem-Jacobsen, Vladimir Todorov, José Flich, José Silla, Tobias Bjerregaard
2012	J	`jnl`	Special issue on Communication Architectures for Scalable Systems. J. Parallel Distributed Comput. José Flich, Scott Pakin, Craig B. Stunkel
2012	—	`conf`	Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip. NOCS Qiaoyan Yu, José Cano, José Flich, Paul Ampadu
2011	J	`jnl`	A Communication-Driven Routing Technique for Application-Specific NoCs. Int. J. Parallel Program. Rafael Tornero, Juan Manuel Orduña, Andres Mejia, José Flich, José Duato
2011	B	`conf`	A Distributed Switch Architecture for On-Chip Networks. ICPP Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato
2011	Misc	`conf`	A fast centralized computation routing algorithm for self-configuring NoC systems. HiPC Francisco Triviño, Francisco José Alfaro, José L. Sánchez, José Flich
2011	J	`jnl`	A low-latency modular switch for CMP systems. Microprocess. Microsystems Antoni Roca, José Flich, Federico Silla, José Duato
2011	—	`conf`	A power-efficient network on-chip topology. INA-OCMC@HiPEAC J. Camacho, José Flich, José Duato, Hans Eberle, Wladek Olesinski
2011	—	`conf`	CASS Introduction. IPDPS Workshops José Flich, Scott Pakin, Craig B. Stunkel
2011	J	`jnl`	Characterizing the impact of process variation on 45 nm NoC-based CMPs. J. Parallel Distributed Comput. Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato
2011	B	`conf`	Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks. ICPP Jesús Escudero-Sahuquillo, Ernst Gunnar Gran, Pedro Javier García, José Flich, Tor Skeie, Olav Lysne, Francisco J. Quiles, José Duato
2011	J	`jnl`	Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato
2011	J	`jnl`	Cost-effective queue schemes for reducing head-of-line blocking in fat-trees. Concurr. Comput. Pract. Exp. Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato
2011	—	`conf`	Efficient routing implementation in complex systems-on-chip. NOCS José Cano, José Flich, José Duato, Marcello Coppola, Riccardo Locatelli
2011	J	`jnl`	Fault-Tolerant Vertical Link Design for Effective 3D Stacking. IEEE Comput. Archit. Lett. Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato
2011	—	`ch.`	Flow Control. Encyclopedia of Parallel Computing José Flich
2011	—	`conf`	HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings. ANCS Jesús Camacho Villanueva, José Flich
2011	B	`conf`	NoC Reconfiguration for CMP Virtualization. NCA Francisco Triviño, Francisco José Alfaro, José L. Sánchez, José Flich
2011	J	`jnl`	OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees. J. Parallel Distributed Comput. Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato
2011	B	`conf`	PC-Mesh: A Dynamic Parallel Concentrated Mesh. ICPP Jesús Camacho Villanueva, José Flich, Antoni Roca, José Duato
2011	—	`ed.`	Proceedings of the Fifth International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC '11, Heraklion, Greece, January 23, 2011 INA-OCMC@HiPEAC José Flich, Davide Bertozzi, Tor Skeie, Daniele Ludovici
2011	—	`conf`	Spidergon STNoC design flow. NOCS Florentine Dubois, José Cano, Marcello Coppola, José Flich, Frédéric Pétrot
2011	—	`ch.`	Switch Architecture. Encyclopedia of Parallel Computing José Flich
2011	C	`conf`	Towards an Efficient NoC Topology through Multiple Injection Ports. DSD Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Wladek Olesinski
2011	J	`jnl`	Virtualizing network-on-chip resources in chip-multiprocessors. Microprocess. Microsystems Francisco Triviño, José L. Sánchez, Francisco José Alfaro, José Flich
2010	C	`conf`	A Latency-Efficient Router Architecture for CMP Systems. DSD Antoni Roca, José Flich, Federico Silla, José Duato
2010	—	`conf`	Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. NOCS Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato
2010	J	`jnl`	Buffer Management Strategies to Reduce HoL Blocking. IEEE Trans. Parallel Distributed Syst. Teresa Nachiondo Frinós, José Flich, José Duato
2010	B	`conf`	Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing. ICPADS Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato
2010	—	`conf`	High Performance Networks. Euro-Par (2) José Flich, Alfonso Urso, Ulrich Brüning, Giuseppe Di Fatta
2010	—	`conf`	Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. NOCS Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato
2010	Misc	`conf`	VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. HiPC Antoni Roca, José Flich, Federico Silla, José Duato
2010	—	`conf`	Welcome to CAC/SSPS 2010. IPDPS Workshops Scott Pakin, Craig B. Stunkel, José Flich, Henrique Andrade, Vibhore Kumar, Deepak S. Turaga
2009	J	`jnl`	A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination. IEEE Trans. Parallel Distributed Syst. Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, José Flich, Francisco J. Quiles, José Duato
2009	—	`conf`	A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors. NoCArc@MICRO Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Nils Gura, Wladek Olesinski
2009	—	`conf`	Dependability Analysis of a Fault-Tolerant Network Reconfiguring Strategy. Euro-Par Vicente Chirivella, Rosa Alcover, José Flich, José Duato
2009	J	`jnl`	Efficient implementation of distributed routing algorithms for NoCs. IET Comput. Digit. Tech. Samuel Rodrigo, Simone Medardoni, José Flich, Davide Bertozzi, José Duato
2009	—	`conf`	Flexible DOR routing for virtualization of multicore chips. SoC Tor Skeie, Frank Olaf Sem-Jacobsen, Samuel Rodrigo, José Flich, Davide Bertozzi, Simone Medardoni
2009	J	`jnl`	Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Trans. Very Large Scale Integr. Syst. Andres Mejia, Maurizio Palesi, José Flich, Shashi Kumar, Pedro López, Rickard Holsmark, José Duato
2009	—	`conf`	Yield-oriented evaluation methodology of network-on-chip routing implementations. SoC Samuel Rodrigo, Carles Hernández, José Flich, Federico Silla, José Duato, Simone Medardoni, Davide Bertozzi, Andres Mejia, Donglai Dai
2008	—	`conf`	An Efficient Implementation of Distributed Routing Algorithms for NoCs. NOCS José Flich, Samuel Rodrigo, José Duato
2008	J	`jnl`	An Efficient and Deadlock-Free Network Reconfiguration Protocol. IEEE Trans. Computers Olav Lysne, José Miguel Montañana, José Flich, José Duato, Timothy Mark Pinkston, Tor Skeie
2008	C	`conf`	CART: Communication-Aware Routing Technique for Application-Specific NoCs. DSD Rafael Tornero, Juan Manuel Orduña, Andres Mejia, José Flich, José Duato
2008	A*	`conf`	Efficient unicast and multicast support for CMPs. MICRO Samuel Rodrigo, José Flich, José Duato, Mark Hummel
2008	A	`conf`	Epoch-based reconfiguration: Fast, simple, and effective dynamic network reconfiguration. IPDPS José Miguel Montañana, José Flich, José Duato
2008	Misc	`conf`	FBICM: Efficient Congestion Management for High-Performance Networks Using Distributed Deterministic Routing. HiPC Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato
2008	A	`conf`	High-radix crossbar switches enabled by proximity communication. SC Hans Eberle, Pedro Javier García, José Flich, José Duato, Robert J. Drost, Nils Gura, David Hopkins, Wladek Olesinski
2008	J	`jnl`	Logic-Based Distributed Routing for NoCs. IEEE Comput. Archit. Lett. José Flich, José Duato
2008	Misc	`conf`	On the Potential of NoC Virtualization for Multicore Chips. CISIS José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne
2008	J	`jnl`	On the Potential of NoC Virtualization for Multicore Chips. Scalable Comput. Pract. Exp. José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne
2008	B	`conf`	On the Potentials of Segment-Based Routing for NoCs. ICPP Andres Mejia, José Flich, José Duato
2008	—	`conf`	Topic 13: High-Performance Networks. Euro-Par Tor Skeie, Daniel Ortega, José Flich, Raimir Holanda
2007	C	`conf`	Boosting Ethernet Performance by Segment-Based Routing. PDP Andres Mejia, José Flich, José Duato, Sven-Arne Reinemo, Tor Skeie
2007	—	`conf`	Integrated QoS Provision and Congestion Management for Interconnection Networks. Euro-Par Alejandro Martínez-Vicente, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, José Flich, Francisco J. Quiles, José Duato
2007	B	`conf`	RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management. ICPP Gaspar Mora, Pedro Javier García, José Flich, José Duato
2007	—	`conf`	Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips. NOCS José Flich, Andres Mejia, Pedro López, José Duato
2007	Misc	`conf`	Understanding cache hierarchy interactions with a program-driven simulator. WCAE Leticia Pascual, Alejandro Torrentí, Julio Sahuquillo, José Flich
2006	J	`jnl`	A Routing Methodology for Achieving Fault Tolerance in Direct Networks. IEEE Trans. Computers María Engracia Gómez, Nils Agne Nordbotten, José Flich, Pedro López, Antonio Robles, José Duato, Tor Skeie, Olav Lysne
2006	—	`conf`	Destination-Based HoL Blocking Elimination. ICPADS (1) Teresa Nachiondo Frinós, José Flich, José Duato
2006	J	`jnl`	Efficient, Scalable Congestion Management for Interconnection Networks. IEEE Micro Pedro Javier García, Francisco J. Quiles, José Flich, José Duato, Ian Johnson, Finbar Naven
2006	B	`conf`	RECN-DD: A Memory-Efficient Congestion Management Technique for Advanced Switching. ICPP Pedro Javier García, Francisco J. Quiles, José Flich, José Duato, Ian Johnson, Finbar Naven
2006	—	`conf`	Reachability-Based Fault-Tolerant Routing. ICPADS (1) José Miguel Montañana, José Flich, Antonio Robles, José Duato
2006	A	`conf`	Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori. IPDPS Andres Mejia, José Flich, José Duato, Sven-Arne Reinemo, Tor Skeie
2006	—	`conf`	Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support. Euro-Par Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, José Flich, Francisco J. Quiles, José Duato
2006	—	`conf`	Towards an efficient switch architecture for high-radix switches. ANCS Gaspar Mora, José Flich, José Duato, Pedro López, Elvira Baydal, Olav Lysne
2005	A*	`conf`	A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks. HPCA José Duato, Ian Johnson, José Flich, Finbar Naven, Pedro Javier García, Teresa Nachiondo Frinós
2005	—	`conf`	A Scalable Methodology for Computing Fault-Free Paths in InfiniBand Torus Networks. ISHPC José Miguel Montañana, José Flich, Antonio Robles, José Duato
2005	—	`conf`	Cost / Performance Trade-Offs and Fairness Evaluation of Queue Mapping Policies. Euro-Par Teresa Nachiondo Frinós, José Flich, José Duato, Mitchell Gusat
2005	—	`conf`	Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture. HiPEAC Pedro Javier García, José Flich, José Duato, Ian Johnson, Francisco J. Quiles, Finbar Naven
2005	A	`conf`	Efficient Reduction of HOL Blocking in Multistage Networks. IPDPS Teresa Nachiondo Frinós, José Flich, José Duato
2005	J	`jnl`	Enforcing in-order packet delivery in system area networks with adaptive routing. J. Parallel Distributed Comput. Michihiro Koibuchi, Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato
2005	A	`conf`	In-Order Packet Delivery in Interconnection Networks using Adaptive Routing. IPDPS Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato, Michihiro Koibuchi
2005	—	`conf`	On the Correct Sizing on Meshes Through an Effective Congestion Management Strategy. Euro-Par Pedro Javier García, José Flich, José Duato, Francisco J. Quiles, Ian Johnson, Finbar Naven
2005	C	`conf`	Studying the Effect of the Design Parameters on the Interconnection Network Performance in NOWs. PDP Raúl Martínez, José L. Sánchez, Francisco José Alfaro, Vicente Chirivella, José Flich
2004	C	`conf`	A Cost-Effective Technique to Reduce HOL Blocking in Single-Stage and Multistage Switch Fabrics. PDP José Duato, José Flich, Teresa Nachiondo Frinós
2004	C	`conf`	A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes. NPC Nils Agne Nordbotten, María Engracia Gómez, José Flich, Pedro López, Antonio Robles, Tor Skeie, Olav Lysne, José Duato
2004	Misc	`conf`	A New Adaptive Fault-Tolerant Routing Methodology for Direct Networks. HiPC María Engracia Gómez, José Duato, José Flich, Pedro López, Antonio Robles, Nils Agne Nordbotten, Tor Skeie, Olav Lysne
2004	A	`conf`	A Transition-Based Fault-Tolerant Routing Methodology for InfiniBand Networks. IPDPS José Miguel Montañana, José Flich, Antonio Robles, Pedro López, José Duato
2004	B	`conf`	An Effective Fault-Tolerant Routing Methodology for Direct Networks. ICPP María Engracia Gómez, José Flich, Pedro López, Antonio Robles, José Duato, Nils Agne Nordbotten, Olav Lysne, Tor Skeie
2004	J	`jnl`	An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori. IEEE Comput. Archit. Lett. María Engracia Gómez, José Duato, José Flich, Pedro López, Antonio Robles, Nils Agne Nordbotten, Olav Lysne, Tor Skeie
2004	J	`jnl`	Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction. IEEE Comput. Archit. Lett. Jeffrey M. Stine, Nicholas P. Carter, José Flich
2004	B	`conf`	LASH-TOR: A Generic Transition-Oriented Routing Algorithm. ICPADS Tor Skeie, Olav Lysne, José Flich, Pedro López, Antonio Robles, José Duato
2004	Misc	`conf`	Simple Deadlock-Free Dynamic Network Reconfiguration. HiPC Olav Lysne, José Miguel Montañana, Timothy Mark Pinkston, José Duato, Tor Skeie, José Flich
2003	J	`jnl`	Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing. IEEE Trans. Computers José Flich, Pedro López, Manuel P. Malumbres, José Duato, Tomas Rokicki
2003	—	`conf`	Low-Fragmentation Mapping Strategies for Linear Forwarding Tables in InfiniBand Euro-Par Pedro López, José Flich, Antonio Robles
2003	A	`conf`	Performance Evaluation of COWs under Real Parallel Application. IPDPS José Carlos Sancho, Juan Carlos Martínez, Antonio Robles, Pedro López, José Flich, José Duato
2003	B	`conf`	Routing in InfiniBandTM Torus Network Topologie. ICPP José Carlos Sancho, Antonio Robles, Pedro López, José Flich, José Duato
2003	C	`conf`	Supporting Adaptive Routing in InfiniBand Networks. PDP Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato
2003	A	`conf`	Supporting Fully Adaptive Routing in InfiniBand Networks. IPDPS Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato
2003	J	`jnl`	Supporting adaptive routing in IBA switches. J. Syst. Archit. Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato
2003	A	`conf`	VOQSW: A Methodology to Reduce HOL Blocking in InfiniBand Networks. IPDPS María Engracia Gómez, José Flich, Antonio Robles, Pedro López, José Duato
2002	A	`conf`	Analyzing the Influence of Virtual Lanes on the Performance of InfiniBand Networks. IPDPS José Carlos Sancho, José Flich, Antonio Robles, Pedro López, José Duato
2002	J	`jnl`	Boosting the Performance of Myrinet Networks. IEEE Trans. Parallel Distributed Syst. José Flich, Pedro López, Manuel P. Malumbres, José Duato
2002	J	`jnl`	Boosting the Performance of Myrinet Networks. IEEE Trans. Parallel Distributed Syst. José Flich, Pedro López, Manuel P. Malumbres, José Duato
2002	B	`conf`	Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks. ICPP José Carlos Sancho, Antonio Robles, José Flich, Pedro López, José Duato
2002	A	`conf`	Evaluation of Alternative Arbitration Policies for Myrinet Switches. IPDPS Pedro Javier García, M. D. Mora, Francisco José Alfaro, José L. Sánchez, José Flich
2002	—	`conf`	Evaluation of Routing Algorithms for InfiniBand Networks (Research Note). Euro-Par María Engracia Gómez, José Flich, Antonio Robles, Pedro López, José Duato
2002	—	`conf`	Improving InfiniBand Routing through Multiple Virtual Networks. ISHPC José Flich, Pedro López, José Carlos Sancho, Antonio Robles, José Duato
2002	C	`conf`	Removing the Latency Overhead of the ITB Mechanism in COWs with Source Routing. PDP José Flich, Manuel P. Malumbres, Pedro López, José Duato
2001	A	`conf`	A First Implementation of In-Transit Buffers on Myrinet GM Software. IPDPS Salvador Coll, José Flich, Manuel P. Malumbres, Pedro López, José Duato, Francisco J. Mora
2001	B	`conf`	Deadlock-Free Routing in InfiniBand through Destination Renaming. ICPP Pedro López, José Flich, José Duato
2001	A	`conf`	Improving Network Performance by Reducing Network Contention in Source-Based COWs with a Low Path-Computation Overhead. IPDPS José Flich, Pedro López, Manuel P. Malumbres, José Duato, Tomas Rokicki
2000	—	`conf`	Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing. ISHPC José Flich, Pedro López, Manuel P. Malumbres, José Duato, Tomas Rokicki
2000	A	`conf`	Improving Routing Performance in Myrinet Networks. IPDPS José Flich, Manuel P. Malumbres, Pedro López, José Duato
2000	B	`conf`	Improving the Performance of Regular Networks with Source Routing. ICPP José Flich, Pedro López, Manuel P. Malumbres, José Duato
2000	A	`conf`	Performance evaluation of a new routing strategy for irregular networks with source routing. ICS José Flich, Manuel P. Malumbres, Pedro López, José Duato
1999	B	`conf`	Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation. ICPP José Flich, Manuel P. Malumbres, Pedro López, José Duato
1998	—	`conf`	Edinet: An Execution Driven Interconnection Network Simulator for DSM Systems. Computer Performance Evaluation (Tools) José Flich, Pedro López, Manuel P. Malumbres, José Duato