Joshua Liang

14 papers C 2Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2022 C conf
Design Considerations for Time-Modulated Injection-Locked Phase Interpolators and Rotators.
ISCAS
Yifan Zhang, Joshua Liang, Tony Chan Carusone
2019 — conf
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.
ISSCC
Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto
2018 J jnl
Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.
IEEE J. Solid State Circuits
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
2018 J jnl
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR.
IEEE J. Solid State Circuits
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
2017 — conf
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.
ISSCC
Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
2017 — conf
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance.
ISSCC
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi
2017 J jnl
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.
IEEE J. Solid State Circuits
Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi
2017 — conf
Jitter injection for on-chip jitter measurement in PI-based CDRs.
CICC
Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi
2015 J jnl
A 3x blind ADC-based CDR for a 20 dB loss channel.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2015 J jnl
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs.
IEEE J. Solid State Circuits
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2014 — conf
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.
VLSIC
Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013 J jnl
A Blind Baud-Rate ADC-Based CDR.
IEEE J. Solid State Circuits
Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2013 — conf
A blind baud-rate ADC-based CDR.
ISSCC
Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura
2010 C conf
A frequency-scalable 15-bit incremental ADC for low power sensor applications.
ISCAS
Joshua Liang, David A. Johns