Joseph Zambreno

123 papers A* 2A 6B 9C 13Misc 13Journal 39Unranked 40

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	An Instruction-Set-Based Processor Design for Scalable Post-Quantum Cryptography: A Case Study with Baby Kyber. VLSID Ramyavani P, Radhanath Mishra, Abhiram Karanam, Amit Kumar Panda, G. Geethakumari, Joseph Zambreno, Subhendu Kumar Sahoo
2023	—	`conf`	An FPGA Implementation of SipHash. IPDPS Workshops Benjamin Welte, Joseph Zambreno
2023	J	`jnl`	Efficient Unmanned Aerial Systems Navigation With Collision Avoidance in Dense Urban Environments. IEEE Trans. Intell. Transp. Syst. Joshua R. Bertram, Joseph Zambreno, Peng Wei
2022	J	`jnl`	A Fast Markov Decision Process-Based Algorithm for Collision Avoidance in Urban Air Mobility. IEEE Trans. Intell. Transp. Syst. Joshua R. Bertram, Peng Wei, Joseph Zambreno
2022	J	`jnl`	Reverse Engineering Controller Area Network Messages Using Unsupervised Machine Learning. IEEE Consumer Electron. Mag. Uchenna Ezeobi, Habeeb Olufowobi, Clinton Young, Joseph Zambreno, Gedare Bloom
2021	—	`conf`	An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers. ASAP Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
2021	J	`jnl`	Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
2020	J	`jnl`	CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks. J. Signal Process. Syst. Saunak Saha, Henry Duwe, Joseph Zambreno
2020	—	`conf`	Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2. FORMATS Brian Kempa, Pei Zhang, Phillip H. Jones, Joseph Zambreno, Kristin Yvonne Rozier
2020	—	`conf`	ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation. ASAP Mohammad Pivezhandi, Phillip H. Jones, Joseph Zambreno
2020	J	`jnl`	SAIDuCANT: Specification-Based Automotive Intrusion Detection Using Controller Area Network (CAN) Timing. IEEE Trans. Veh. Technol. Habeeb Olufowobi, Clinton Young, Joseph Zambreno, Gedare Bloom
2020	J	`jnl`	Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict. CoRR Joshua R. Bertram, Peng Wei, Joseph Zambreno
2020	—	`conf`	Towards Reverse Engineering Controller Area Network Messages Using Machine Learning. WF-IoT Clinton Young, Jordan Svoboda, Joseph Zambreno
2019	—	`conf`	An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators. ASAP Saunak Saha, Henry Duwe, Joseph Zambreno
2019	Misc	`conf`	Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. FCCM Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers
2019	—	`conf`	Anomaly Detection Approach Using Adaptive Cumulative Sum Algorithm for Controller Area Network. AutoSec@CODASPY Habeeb Olufowobi, Uchenna Ezeobi, Eric Muhati, Gaylon Robinson, Clinton Young, Joseph Zambreno, Gedare Bloom
2019	—	`conf`	Automotive Intrusion Detection Based on Constant CAN Message Frequencies Across Vehicle Driving Modes. AutoSec@CODASPY Clinton Young, Habeeb Olufowobi, Gedare Bloom, Joseph Zambreno
2019	—	`conf`	Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. ICESS Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
2019	J	`jnl`	Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. CoRR Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
2019	J	`jnl`	Survey of Automotive Controller Area Network Intrusion Detection Systems. IEEE Des. Test Clinton Young, Joseph Zambreno, Habeeb Olufowobi, Gedare Bloom
2018	B	`conf`	A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. FPL Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
2018	J	`jnl`	ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits. IEEE Trans. Computers Alex Grieve, Michael Davies, Phillip H. Jones, Joseph Zambreno
2018	—	`conf`	An FPGA-based Hardware Accelerator for Iris Segmentation. ReConFig Joe Avey, Phillip H. Jones, Joseph Zambreno
2018	—	`conf`	HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. ReConFig Matthew Cauwels, Joseph Zambreno, Phillip H. Jones
2018	B	`conf`	Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection. ICPP Xian Zhu, Robert Wernsman, Joseph Zambreno
2018	A	`conf`	Work-in-Progress: Real-Time Modeling for Intrusion Detection in Automotive Controller Area Network. RTSS Habeeb Olufowobi, Gedare Bloom, Clinton Young, Joseph Zambreno
2017	—	`conf`	A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization. IPDPS Workshops Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
2017	—	`conf`	An embedded scalable linear model predictive hardware-based controller using ADMM. ASAP Pei Zhang, Joseph Zambreno, Phillip H. Jones
2017	J	`jnl`	The design and integration of a software configurable and parallelized coprocessor architecture for LQR control. J. Parallel Distributed Comput. Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones
2016	J	`jnl`	A Reconfigurable Architecture for the Detection of Strongly Connected Components. ACM Trans. Reconfigurable Technol. Syst. Osama G. Attia, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno
2016	C	`conf`	Evidence-based planning to broaden the participation of women in electrical and computer engineering. FIE Diane T. Rover, Joseph Zambreno, Mani Mina, Phillip H. Jones, Lora Leigh Chrystal
2016	C	`conf`	ONAC: Optimal number of active cores detector for energy efficient GPU computing. ICCD Xian Zhu, Mihir Awatramani, Diane T. Rover, Joseph Zambreno
2016	C	`conf`	Parallelizing Latent Semantic Indexing using an FPGA-based architecture. ICCD Xinying Wang, Joseph Zambreno
2016	—	`conf`	Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling. IPDPS Workshops Aaron Mills, Phillip H. Jones, Joseph Zambreno
2016	J	`jnl`	RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing. IEEE Trans. Parallel Distributed Syst. Chad Nelson, Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
2015	J	`jnl`	A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. SIGARCH Comput. Archit. News Xinying Wang, Phillip H. Jones, Joseph Zambreno
2015	J	`jnl`	A Scalable Unsegmented Multiport Memory for FPGA-Based Systems. Int. J. Reconfigurable Comput. Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
2015	—	`conf`	A multi-phase approach to floating-point compression. EIT Kevin R. Townsend, Joseph Zambreno
2015	—	`conf`	A project-based embedded systems design course using a reconfigurable SoC platform. MSE Daniel Roggow, Paul Uhing, Phillip H. Jones, Joseph Zambreno
2015	—	`conf`	A software configurable and parallelized coprocessor architecture for LQR control. ReConFig Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones
2015	B	`conf`	A software configurable coprocessor-based state-space controller. FPL Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones
2015	—	`conf`	Accelerating all-pairs shortest path using a message-passing reconfigurable architecture. ReConFig Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno
2015	J	`jnl`	An FPGA Architecture for the Recovery of WPA/WPA2 Keys. J. Circuits Syst. Comput. Tyler Johnson, Daniel Roggow, Phillip H. Jones, Joseph Zambreno
2015	B	`conf`	Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications. PACT Mihir Awatramani, Xian Zhu, Joseph Zambreno, Diane T. Rover
2015	J	`jnl`	Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform. Microprocess. Microsystems Madhu Monga, Daniel Roggow, Manoj Karkee, Song Sun, Lakshmi Kiran Tondehal, Brian L. Steward, Atul G. Kelkar, Joseph Zambreno
2015	—	`conf`	k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator. EIT Kevin R. Townsend, Song Sun, Tyler Johnson, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
2014	—	`conf`	A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach. ISVLSI Xinying Wang, Phillip H. Jones, Joseph Zambreno
2014	C	`conf`	A high performance systolic architecture for k-NN classification. MEMOCODE Kevin Townsend, Phillip H. Jones, Joseph Zambreno
2014	Misc	`conf`	An Efficient Architecture for Floating-Point Eigenvalue Decomposition. FCCM Xinying Wang, Joseph Zambreno
2014	—	`conf`	An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition. IPDPS Workshops Xinying Wang, Joseph Zambreno
2014	J	`jnl`	An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis. IEEE Embed. Syst. Lett. Sudhanshu Vyas, Chetan Kumar Ng, Joseph Zambreno, Christopher D. Gill, Ron Cytron, Phillip H. Jones
2014	C	`conf`	Cache design for mixed criticality real-time systems. ICCD N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2014	—	`conf`	CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search. IPDPS Workshops Osama G. Attia, Tyler Johnson, Kevin Townsend, Phillip H. Jones, Joseph Zambreno
2014	J	`jnl`	Hardware Architecture for Video Authentication Using Sensor Pattern Noise. IEEE Trans. Circuits Syst. Video Technol. Amit Pande, Shaxun Chen, Prasant Mohapatra, Joseph Zambreno
2014	J	`jnl`	Hardware-software architecture for priority queue management in real-time and embedded systems. Int. J. Embed. Syst. N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2014	—	`conf`	Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications. ICPP Workshops Mihir Awatramani, Joseph Zambreno, Diane T. Rover
2014	—	`conf`	Towards scalable monitoring and maintenance of rechargeable batteries. EIT Aaron Mills, Joseph Zambreno
2013	J	`jnl`	A chaotic encryption scheme for real-time embedded systems: design and implementation. Telecommun. Syst. Amit Pande, Joseph Zambreno
2013	Misc	`conf`	A multi-faceted approach to FPGA-based Trojan circuit detection. VTS Michael Patterson, Aaron Mills, Ryan A. Scheel, Julie Tillman, Evan Dye, Joseph Zambreno
2013	J	`jnl`	Hardware architectural support for control systems and sensor processing. ACM Trans. Embed. Comput. Syst. Sudhanshu Vyas, Adwait Gupte, Christopher D. Gill, Ron K. Cytron, Joseph Zambreno, Phillip H. Jones
2013	C	`conf`	Increasing GPU throughput using kernel interleaved thread block scheduling. ICCD Mihir Awatramani, Joseph Zambreno, Diane T. Rover
2013	Misc	`conf`	Polarity Trend Analysis of Public Sentiment on YouTube. COMAD Amar Krishna, Joseph Zambreno, Sandeep Krishnan
2013	—	`conf`	Reduce, Reuse, Recycle (R ASAP Kevin Townsend, Joseph Zambreno
2013	Misc	`conf`	Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms. ICCS Chetan Kumar Ng, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2013	J	`jnl`	Securing Multimedia Content Using Joint Compression and Encryption. IEEE Multim. Amit Pande, Prasant Mohapatra, Joseph Zambreno
2012	J	`jnl`	An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. Song Sun, Madhu Monga, Phillip H. Jones, Joseph Zambreno
2012	C	`conf`	Design and evaluation of a delay-based FPGA Physically Unclonable Function. ICCD Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno
2012	—	`book`	Embedded Multimedia Security Systems - Algorithms and Architectures. Amit Pande, Joseph Zambreno
2012	Misc	`conf`	Improving System Predictability and Performance via Hardware Accelerated Data Structures. ICCS Chetan Kumar Ng, Sudhanshu Vyas, Jonathan A. Shidal, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2012	J	`jnl`	Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression. ACM Trans. Embed. Comput. Syst. Amit Pande, Joseph Zambreno
2012	Misc	`conf`	Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform. ICCS Madhu Monga, Manoj Karkee, Song Sun, Lakshmi Kiran Tondehal, Brian L. Steward, Atul G. Kelkar, Joseph Zambreno
2012	C	`conf`	Shepard: A fast exact match short read aligner. MEMOCODE Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno
2012	J	`jnl`	The secure wavelet transform. J. Real Time Image Process. Amit Pande, Joseph Zambreno
2011	J	`jnl`	A case study in hardware Trojan design and implementation. Int. J. Inf. Sec. Alex Baumgarten, Michael Steffen, Matthew Clausman, Joseph Zambreno
2011	—	`conf`	Architectures for Simultaneous Coding and Encryption Using Chaotic Maps. ISVLSI Amit Pande, Joseph Zambreno, Prasant Mohapatra
2011	C	`conf`	Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. ICCD Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno
2011	J	`jnl`	Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining. IEEE Trans. Parallel Distributed Syst. Song Sun, Joseph Zambreno
2011	J	`jnl`	Efficient mapping and acceleration of AES on custom multi-core architectures. Concurr. Comput. Pract. Exp. Amit Pande, Joseph Zambreno
2011	—	`conf`	Teaching graphics processing and architecture using a hardware prototyping approach. MSE Michael Steffen, Phillip H. Jones, Joseph Zambreno
2011	C	`conf`	Using Chaotic Maps for Encrypting Image and Video Content. ISM Amit Pande, Prasant Mohapatra, Joseph Zambreno
2010	Misc	`conf`	A Reconfigurable Architecture for Secure Multimedia Delivery. VLSI Design Amit Pande, Joseph Zambreno
2010	—	`conf`	A hardware pipeline for accelerating ray traversal algorithms on streaming processors. SASP Michael Steffen, Joseph Zambreno
2010	C	`conf`	CANSCID-CUDA. MEMOCODE Michael Steffen, Veerendra Allada, Phillip H. Jones, Joseph Zambreno
2010	A	`conf`	Detecting/preventing information leakage on the memory bus due to malicious hardware. DATE Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary
2010	A*	`conf`	Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels. MICRO Michael Steffen, Joseph Zambreno
2010	J	`jnl`	Preventing IC Piracy Using Reconfigurable Logic Barriers. IEEE Des. Test Comput. Alex Baumgarten, Akhilesh Tyagi, Joseph Zambreno
2010	J	`jnl`	Reconfigurable hardware implementation of a modified chaotic filter bank scheme. Int. J. Embed. Syst. Amit Pande, Joseph Zambreno
2009	—	`conf`	An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform. ISVLSI Amit Pande, Joseph Zambreno
2009	—	`conf`	Architectural Support for Automated Software Attack Detection, Recovery, and Prevention. CSE (2) Jesse Sathre, Alex Baumgarten, Joseph Zambreno
2009	J	`jnl`	Demonstrable differential power analysis attacks on real-world FPGA-based embedded systems. Integr. Comput. Aided Eng. Song Sun, Zijun Yan, Joseph Zambreno
2009	—	`conf`	Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure. TPCG Michael Steffen, Joseph Zambreno
2009	—	`conf`	Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores. CSE (2) Amit Pande, Joseph Zambreno
2009	—	`conf`	Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems. CSE (2) Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno
2009	—	`conf`	Hardware-enforced fine-grained isolation of untrusted code. SecuCode@CCS Eugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno
2009	J	`jnl`	Providing secure execution environments with a last line of defense against Trojan circuit attacks. Comput. Secur. Gedare Bloom, Bhagirath Narahari, Rahul Simha, Joseph Zambreno
2008	—	`conf`	A Reconfigurable Platform for Frequent Pattern Mining. ReConFig Song Sun, Michael Steffen, Joseph Zambreno
2008	A	`conf`	An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System. DATE Abhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary
2008	J	`jnl`	An FPGA-Based Network Intrusion Detection Architecture. IEEE Trans. Inf. Forensics Secur. Abhishek Das, David Nguyen, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary
2008	J	`jnl`	Automated software attack recovery using rollback and huddle. Des. Autom. Embed. Syst. Jesse Sathre, Joseph Zambreno
2008	—	`conf`	Design and analysis of efficient reconfigurable wavelet filters. EIT Amit Pande, Joseph Zambreno
2008	A*	`conf`	Evaluating the effects of cache redundancy on profit. MICRO Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary
2008	—	`conf`	Experiments in attacking FPGA-based embedded systems using differential power analysis. EIT Song Sun, Zijun Yan, Joseph Zambreno
2008	J	`jnl`	Microarchitectures for Managing Chip Revenues under Process Variations. IEEE Comput. Archit. Lett. Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary
2008	B	`conf`	Mining Association Rules with systolic trees. FPL Song Sun, Joseph Zambreno
2008	B	`conf`	Polymorphic wavelet architectures using reconfigurable hardware. FPL Amit Pande, Joseph Zambreno
2007	—	`conf`	Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction. FPT Sailesh Pati, Ramanathan Narayanan, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno
2007	A	`conf`	Interactive presentation: An FPGA implementation of decision tree classification. DATE Ramanathan Narayanan, Daniel Honbo, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno
2007	J	`jnl`	Microarchitectures for Managing Chip Revenues under Process Variations. IEEE Comput. Archit. Lett. Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary
2007	Misc	`conf`	Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads. International Conference on Computational Science (3) Ramanathan Narayanan, Berkin Özisikyilmaz, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno
2006	—	`conf`	An Architectural Characterization Study of Data Mining and Bioinformatics Workloads. IISWC Berkin Özisikyilmaz, Ramanathan Narayanan, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary
2006	J	`jnl`	High-Performance Software Protection Using Reconfigurable Architectures. Proc. IEEE Joseph Zambreno, Daniel Honbo, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari
2006	—	`conf`	MineBench: A Benchmark Suite for Data Mining Workloads. IISWC Ramanathan Narayanan, Berkin Özisikyilmaz, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary
2005	C	`conf`	CODESSEAL: Compiler/FPGA Approach to Secure Applications. ISI Olga Gelbart, Paul Ott, Bhagirath Narahari, Rahul Simha, Alok N. Choudhary, Joseph Zambreno
2005	Misc	`conf`	Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures. FCCM Joseph Zambreno, Daniel Honbo, Alok N. Choudhary
2005	C	`conf`	Performance Study of a Compiler/Hardware Approach to Embedded Systems Security. ISI Kripashankar Mohan, Bhagirath Narahari, Rahul Simha, Paul Ott, Alok N. Choudhary, Joseph Zambreno
2005	J	`jnl`	SAFE-OPS: An approach to embedded software security. ACM Trans. Embed. Comput. Syst. Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari, Nasir D. Memon
2004	A	`conf`	Addressing application integrity attacks using a reconfigurable architecture. FPGA Joseph Zambreno, Rahul Simha, Alok N. Choudhary
2004	B	`conf`	Design and Evaluation of an FPGA Architecture for Software Protection. FPL Joseph Zambreno
2004	B	`conf`	Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. FPL Joseph Zambreno, David Nguyen, Alok N. Choudhary
2004	A	`conf`	Flexible Software Protection Using Hardware/Software Codesign Techniques. DATE Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari
2004	B	`conf`	Flow Monitoring in High-Speed Networks with 2D Hash Tables. FPL David Nguyen, Joseph Zambreno, Gokhan Memik
2002	Misc	`conf`	Enhancing Compiler Techniques for Memory Energy Optimizations. EMSOFT Joseph Zambreno, Mahmut T. Kandemir, Alok N. Choudhary
2002	Misc	`conf`	Optimizing inter-nest data locality. CASES Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Joseph Zambreno