Joseph S. Chang

88 papers C 31Journal 32Unranked 25
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 50-MHz Pulse-Width Modulator Embodying Low-Loss Quasi-Dynamic Comparators for Very High-Frequency DC-DC Converters.
IEEE J. Solid State Circuits
Sun-Yang Tay, Victor Adrian, Joseph S. Chang
2025 C conf
A Novel Energy-Efficient Continuous-Time Hysteretic VCO-Based Comparator.
ISCAS
Jinhen Lee, Victor Adrian, Kinglouis Steven Tantra, Bah-Hwee Gwee, Joseph S. Chang
2025 C conf
A Novel High-Accuracy Inductor-Current Estimator for Digitally-Controlled Synchronous DC-DC Buck Converters.
ISCAS
Yanshan Xie, Victor Adrian, Jinhen Lee, Joseph S. Chang
2025 C conf
An Adaptive AI-based Approach to Detect and Protect COTS Systems against Micro-Single-Event-Latchups (μ-SELs) and SELs.
ISCAS
Junkai Zhao, Yin Sun, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang
2025 — conf
An Improved AI-Based Micro-Single-Event-Latchup (Micro-SEL) and SEL Detection in a COTS System Against R/C/L-Induced (Power Management) Distortions.
ICECS
Junkai Zhao, Caoyang Yu, Jiwei Wang, Yin Sun, Tony Zhang, Tong Ge, Kwen-Siong Chong, Wei Shu, Joseph S. Chang
2025 C conf
Live Demonstration: AI-based System Latchup Detection and Protection for COTS Systems.
ISCAS
Yin Sun, Junkai Zhao, Rouli Fang, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang
2025 J jnl
Single-Ended/Differential Wideband Track-and-Hold Amplifier in 22-nm FD-SOI CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst.
Zixian Zheng, Wei Shu, Joseph S. Chang
2024 — conf
A 134-μW 50-MHz Quasi-Dynamic Comparator with A Novel Clock-Free Regenerative Latch.
CICC
Sun-Yang Tay, Victor Adrian, Rouli Fang, Yanshan Xie, Joseph S. Chang
2024 — conf
An Energy-Efficient and High-Accuracy Spiking Neural Network Utilizing Asynchronous CORDIC for On-FPGA STDP Learning.
APCCAS
Shirui Sheng, Kwen-Siong Chong, Jun-Sheng Ng, Zhiping Lin, Joseph S. Chang, Bah-Hwee Gwee
2023 C conf
A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters.
ISCAS
Jinhen Lee, Victor Adrian, Sun-Yang Tay, Yanshan Xie, Bah-Hwee Gwee, Joseph S. Chang
2023 C conf
An Accurate Digital Inductor Current Sensor for Current-Ripple-Based DC-DC Converters.
ISCAS
Yanshan Xie, Victor Adrian, Sun-Yang Tay, Jinhen Lee, Pak Kwong Chan, Joseph S. Chang
2022 J jnl
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks.
IEEE Trans. Very Large Scale Integr. Syst.
Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2022 C conf
A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors.
ISCAS
Sun-Yang Tay, Victor Adrian, Joseph S. Chang, Jinhen Lee, Bah-Hwee Gwee
2022 C conf
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations.
ISCAS
Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2022 C conf
An Integrated DC-DC Converter with Novel Asymmetrical Segmented Power-Stages for Sustained High Power-Efficiencies.
ISCAS
Jinhen Lee, Victor Adrian, Joseph S. Chang, Yin Sun, Sun-Yang Tay
2021 — conf
A 12-W 96.1%-Efficiency eFuse-Based Ultrafast Battery Charger Supporting Wireless and USB Power Inputs.
CICC
Yong Qu, Wei Shu, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang, Yue Li, Zixian Zheng, Joseph S. Chang
2020 C conf
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.
ISCAS
Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2020 J jnl
A Low-Profile High-Efficiency Fast Battery Charger With Unifiable Constant-Current and Constant-Voltage Regulation.
IEEE Trans. Circuits Syst.
Yong Qu, Wei Shu, Lei Qiu, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang, Joseph S. Chang
2020 C conf
Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller.
ISCAS
Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Wei Shu, Joseph S. Chang
2019 — conf
A 30V 2A Real-Time Programmable Solid-State Circuit Breaker with Improved Detection-Speed and Enhanced Power-Efficiency.
ESSCIRC
Yong Qu, Wei Shu, Yang Kang, Joseph S. Chang
2019 J jnl
A Fully Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics With Self-Compensation for Bending: Codesign From Materials, Design, Fabrication, and Applications.
Proc. IEEE
Joseph S. Chang, Tong Ge
2019 — conf
A Monolithic I
CICC
Yong Qu, Wei Shu, Joseph S. Chang
2019 J jnl
Flexible Electronic Skin: From Humanoids to Humans.
Proc. IEEE
Ravinder Dahiya, Deji Akinwande, Joseph S. Chang
2019 C conf
Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design.
ISCAS
Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, Wei Shu, Joseph S. Chang, Bah-Hwee Gwee
2019 — conf
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.
AsianHOST
Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang
2018 J jnl
A 1-GS/s 11-Bit SAR-Assisted Pipeline ADC With 59-dB SNDR in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Qing Liu, Wei Shu, Joseph S. Chang
2018 J jnl
A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range.
IEEE J. Solid State Circuits
Jize Jiang, Wei Shu, Joseph S. Chang
2018 J jnl
A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme.
IEEE Trans. Very Large Scale Integr. Syst.
F. N. U. Juanda, Wei Shu, Joseph S. Chang
2018 — conf
A Circuit for Reducing the Reverse Current in DCM DC-DC Converters.
DSP
Yin Sun, Victor Adrian, Tong Ge, Joseph S. Chang
2018 J jnl
A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Cui Keer, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
2018 C conf
An Air-Core Coupled-Inductor Based Dual-Phase Output Stage for Point-of-Load Converters.
ISCAS
Yong Qu, Wei Shu, Joseph S. Chang
2018 J jnl
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design.
IEEE Trans. Very Large Scale Integr. Syst.
Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang
2018 C conf
Flexible Hybrid Electronics: Review and Challenges.
ISCAS
Tong Ge, Zhou Jia, Joseph S. Chang
2018 C conf
Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters.
ISCAS
Yin Sun, Victor Adrian, Joseph S. Chang
2018 — conf
Single-Event-Transient Resilient Memory for DSP in Space Applications.
DSP
Ne Kyaw Zwa Lwin, H. Sivaramakrishnan, Kwen-Siong Chong, Tong Lin, Wei Shu, Joseph S. Chang
2017 J jnl
A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands.
IEEE Trans. Circuits Syst. II Express Briefs
F. N. U. Juanda, Wei Shu, Joseph S. Chang
2017 J jnl
A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Qing Liu, Wei Shu, Joseph S. Chang
2017 J jnl
A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point.
IEEE J. Solid State Circuits
Jize Jiang, Wei Shu, Joseph S. Chang
2017 J jnl
A Circuits and Systems Perspective of Organic/Printed Electronics: Review, Challenges, and Contemporary and Emerging Design Approaches.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Joseph S. Chang, Antonio F. Facchetti, Robert Reuss
2017 C conf
A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation.
ISCAS
Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
2017 — conf
A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters.
NEWCAS
Cui Keer, Victor Adrian, Yin Sun, Bah-Hwee Gwee, Joseph S. Chang
2017 C conf
A novel high-rate hybrid window ADC design for monolithic digitally-controlled DC-DC converters.
ISCAS
Yin Sun, Victor Adrian, Joseph S. Chang
2017 J jnl
Guest Editorial Organic/Printed Electronics: A Circuits and Systems Perspective.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Joseph S. Chang, Antonio F. Facchetti, Robert Reuss
2017 J jnl
Printed Electronics: Effects of Bending and a Self-Compensation Means.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jia Zhou, Tong Ge, Joseph S. Chang
2017 C conf
Review: A fully-additive printed electronics process with very-low process variations (Bent and unbent substrates) and PDK.
ISCAS
Tong Ge, Jia Zhou, Yang Kang, Joseph S. Chang
2017 J jnl
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.
IEEE Trans. Very Large Scale Integr. Syst.
Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2016 — conf
A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network.
ISIC
Qianqian Liu, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
2016 — conf
A review of audio Class D amplifiers.
ISIC
Yang Kang, Tong Ge, Huiqiao He, Joseph S. Chang
2016 C conf
An investigation of THD of a BTL Class D amplifier.
ISCAS
Tong Ge, Huiqiao He, Jia Zhou, Yang Kang, Joseph S. Chang
2016 C conf
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.
ISCAS
Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang
2016 C conf
Fully-additive printed electronics: Process Development Kit.
ISCAS
Jia Zhou, Tong Ge, Joseph S. Chang
2016 — conf
Substrate thickness effect on transformer.
ISIC
Jia Yu, Tong Ge, Huiqiao He, Joseph S. Chang
2015 — conf
A novel low-power high-efficiency 3-state filterless bang-bang class D amplifier.
ICECS
Huiqiao He, Yang Kang, Jia Yu, Linfei Guo, Tong Ge, Joseph S. Chang
2015 C conf
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline.
ISCAS
Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2015 J jnl
An Ultralow-Power Overcurrent Protection Circuit for Micropower Class D Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs
Linfei Guo, Tong Ge, Joseph S. Chang
2015 C conf
Design of a variable-delay window ADC for switched-mode DC-DC converters.
ISCAS
Yin Sun, Victor Adrian, Joseph S. Chang
2015 C conf
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang
2015 J jnl
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer.
IET Circuits Devices Syst.
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014 J jnl
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014 — conf
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation.
ISIC
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin
2014 — conf
A self-oscillating class D audio amplifier with dual voltage and current feedback.
ISIC
Salma Nashit, Victor Adrian, Cui Keer, Quoc-An Mai, Bah-Hwee Gwee, Joseph S. Chang
2014 — conf
An investigation into the effect of carrier generators on power supply noise in PWM Class D amplifiers.
MWSCAS
Huiqiao He, Tong Ge, Linfei Guo, Joseph S. Chang
2014 — conf
Design of an output stage for high switching frequency DC-DC converters.
ISIC
Tian-Shun Ng, Yin Sun, Victor Adrian, Bah-Hwee Gwee, Joseph S. Chang
2014 — conf
Fully-Additive printed electronics on flexible substrates: A Fully-Additive RFID tag.
MWSCAS
Tong Ge, Joseph S. Chang, Tong Lin, Lei Zhang, Lim Geok Soon
2014 — conf
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips.
APCCAS
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014 — conf
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process.
MWSCAS
Joseph S. Chang, Kwen-Siong Chong, Wei Shu, Tong Lin, Jize Jiang, Ne Kyaw Zwa Lwin, Yang Kang
2014 C conf
Synthesis of asynchronous QDI circuits using synchronous coding specifications.
ISCAS
Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho
2013 C conf
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic.
ISCAS
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2013 J jnl
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive V
IEEE J. Solid State Circuits
Tong Lin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee
2013 C conf
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2013 J jnl
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Kok-Leong Chang, Joseph S. Chang, Bah-Hwee Gwee, Kwen-Siong Chong
2012 C conf
A comparative study on asynchronous Quasi-Delay-Insensitive templates.
ISCAS
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2012 C conf
An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability.
ISCAS
Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2012 — conf
Challenges of printed electronics on flexible substrates.
MWSCAS
Joseph S. Chang, Tong Ge, Edgar Sánchez-Sinencio
2012 — conf
Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques.
ISED
Kwen-Siong Chong, Joseph S. Chang, Idongesit E. Ebong, Yalcin Yilmaz, Pinaki Mazumder
2012 C conf
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2012 J jnl
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors.
IEEE J. Solid State Circuits
Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang
2010 J jnl
A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee
2010 J jnl
Filterless class D amplifiers: power-efficiency and power dissipation.
IET Circuits Devices Syst.
Tong Ge, Joseph S. Chang
2009 J jnl
A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bah-Hwee Gwee, Joseph S. Chang, Yiqiong Shi, Chien-Chung Chua, Kwen-Siong Chong
2009 J jnl
A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids.
IEEE Trans. Circuits Syst. I Regul. Pap.
Victor Adrian, Joseph S. Chang, Bah-Hwee Gwee
2009 J jnl
Bang-Bang Control Class D Amplifiers: Total Harmonic Distortion and Supply Noise.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tong Ge, Joseph S. Chang
2008 J jnl
Bang-Bang Control Class-D Amplifiers: Power-Supply Noise.
IEEE Trans. Circuits Syst. II Express Briefs
Tong Ge, Joseph S. Chang
2007 J jnl
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors.
IEEE J. Solid State Circuits
Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2006 — conf
Optimized Algorithm for Computing Invariants of Ordinary Petri Nets.
ACIS-ICIS
Chong-Fatt Law, Bah-Hwee Gwee, Joseph S. Chang
2000 C conf
An investigation on the parameters affecting total harmonic distortion in class D amplifiers.
ISCAS
Meng Tong Tan, Hock-Chuan Chua, Bah-Hwee Gwee, Joseph S. Chang
1999 — conf
A process-independent threshold voltage inverter-comparator for pulse width modulation applications.
ICECS
Meng Tong Tan, Joseph S. Chang, Yit Chow Tong
1993 J jnl
A micropower-compatible time-multiplexed SC speech spectrum analyzer design.
IEEE J. Solid State Circuits
Joseph S. Chang, Yit Chow Tong