Josep Torrellas

318 papers A* 149A 30B 18C 12Misc 5Journal 67Unranked 33

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	AccelFlow: Orchestrating an On-Package Ensemble of Fine-Grained Accelerators for Microservices. HPCA Jovan Stojkovic, Abraham Farrell, Zhangxiaowen Gong, Christopher J. Hughes, Josep Torrellas
2026	A	`conf`	GRANII: Selection and Ordering of Primitives in GRAph Neural Networks using Input Inspection. CGO Damitha Lenadora, Vimarsh Sathia, Gerasimos Gerogiannis, Serif Yesil, Josep Torrellas, Charith Mendis
2026	J	`jnl`	HEAL: Online Incremental Recovery for Leaderless Distributed Systems Across Persistency Models. CoRR Antonis Psistakis, Burak Ocalan, Fabien Chaix, Ramnatthan Alagappan, Josep Torrellas
2026	A*	`conf`	PhasedStore: Supporting High-Performance Write-Through Cache-Coherence Protocols Under TSO. HPCA Burak Ocalan, Chloe Alverti, Shashwat Jaiswal, Antonis Psistakis, David A. Koufaty, Suyash Mahar, Steven Swanson, Josep Torrellas
2026	J	`jnl`	Towards CXL Resilience to CPU Failures. CoRR Antonis Psistakis, Burak Ocalan, Chloe Alverti, Fabien Chaix, Ramnatthan Alagappan, Josep Torrellas
2025	A*	`conf`	COGNATE: Acceleration of Sparse Tensor Programs on Emerging Hardware using Transfer Learning. ICML Chamika Sudusinghe, Gerasimos Gerogiannis, Damitha Lenadora, Charles Block, Josep Torrellas, Charith Mendis
2025	J	`jnl`	COGNATE: Acceleration of Sparse Tensor Programs on Emerging Hardware using Transfer Learning. CoRR Chamika Sudusinghe, Gerasimos Gerogiannis, Damitha Lenadora, Charles Block, Josep Torrellas, Charith Mendis
2025	—	`conf`	CXLfork: Fast Remote Fork over CXL Fabrics. ASPLOS (2) Chloe Alverti, Stratos Psomadakis, Burak Ocalan, Shashwat Jaiswal, Tianyin Xu, Josep Torrellas
2025	A*	`conf`	Chameleon: Adaptive Caching and Scheduling for Many-Adapter LLM Inference Environments. MICRO Nikoleta Iliakopoulou, Jovan Stojkovic, Chloe Alverti, Tianyin Xu, Hubertus Franke, Josep Torrellas
2025	A*	`conf`	Concord: Rethinking Distributed Coherence for Software Caches in Serverless Environments. HPCA Jovan Stojkovic, Chloe Alverti, Alan Andrade, Nikoleta Iliakopoulou, Hubertus Franke, Tianyin Xu, Josep Torrellas
2025	A*	`conf`	DECA: A Near-Core LLM Decompression Accelerator Grounded on a 3D Roofline Model. MICRO Gerasimos Gerogiannis, Stijn Eyerman, Evangelos Georganas, Wim Heirman, Josep Torrellas
2025	J	`jnl`	DECA: A Near-Core LLM Decompression Accelerator Supporting Out-of-Order Invocation. CoRR Gerasimos Gerogiannis, Stijn Eyerman, Evangelos Georganas, Wim Heirman, Josep Torrellas
2025	A*	`conf`	DynamoLLM: Designing LLM Inference Clusters for Performance and Energy Efficiency. HPCA Jovan Stojkovic, Chaojie Zhang, Íñigo Goiri, Josep Torrellas, Esha Choukse
2025	A*	`conf`	EMT: An OS Framework for New Memory Translation Architectures. OSDI Siyuan Chai, Jiyuan Zhang, Jongyul Kim, Alan Wang, Fan Chung, Jovan Stojkovic, Weiwei Jia, Dimitrios Skarlatos, Josep Torrellas, Tianyin Xu
2025	J	`jnl`	From Colocation to Exfiltration: Practical Cache Side-Channel Attacks in the Modern Public Cloud. IEEE Micro Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas
2025	A*	`conf`	HardHarvest: Hardware-Supported Core Harvesting for Microservices. ISCA Jovan Stojkovic, Chunao Liu, Muhammad Shahbaz, Josep Torrellas
2025	A*	`conf`	MeshSlice: Efficient 2D Tensor Parallelism for Distributed DNN Training. ISCA Hyoungwook Nam, Gerasimos Gerogiannis, Josep Torrellas
2025	A*	`conf`	Micro-MAMA: Multi-Agent Reinforcement Learning for Multicore Prefetching. MICRO Charles Block, Gerasimos Gerogiannis, Josep Torrellas
2025	A*	`conf`	NetSparse: In-Network Acceleration of Distributed Sparse Kernels. MICRO Gerasimos Gerogiannis, Dimitrios Merkouriadis, Charles Block, Annus Zulfiqar, Filippos Tofalos, Muhammad Shahbaz, Josep Torrellas
2025	J	`jnl`	Serving Heterogeneous LoRA Adapters in Distributed LLM Inference Systems. CoRR Shashwat Jaiswal, Shrikara Arun, Anjaly Parayil, Ankur Mallick, Spyros Mastorakis, Alind Khare, Chloe Alverti, Renée St. Amant, Chetan Bansal, Victor Rühle, Josep Torrellas
2025	—	`conf`	TAPAS: Thermal- and Power-Aware Scheduling for LLM Inference in Cloud Platforms. ASPLOS (2) Jovan Stojkovic, Chaojie Zhang, Íñigo Goiri, Esha Choukse, Haoran Qiu, Rodrigo Fonseca, Josep Torrellas, Ricardo Bianchini
2025	J	`jnl`	TAPAS: Thermal- and Power-Aware Scheduling for LLM Inference in Cloud Platforms. CoRR Jovan Stojkovic, Chaojie Zhang, Íñigo Goiri, Esha Choukse, Haoran Qiu, Rodrigo Fonseca, Josep Torrellas, Ricardo Bianchini
2024	J	`jnl`	Chameleon: Adaptive Caching and Scheduling for Many-Adapter LLM Inference Environments. CoRR Nikoleta Iliakopoulou, Jovan Stojkovic, Chloe Alverti, Tianyin Xu, Hubertus Franke, Josep Torrellas
2024	A	`conf`	Distributed-Memory Parallel Algorithms for Sparse Matrix and Sparse Tall-and-Skinny Matrix Multiplication. SC Isuru Ranawaka, Md Taufique Hussain, Charles Block, Gerasimos Gerogiannis, Josep Torrellas, Ariful Azad
2024	J	`jnl`	Distributed-Memory Parallel Algorithms for Sparse Matrix and Sparse Tall-and-Skinny Matrix Multiplication. CoRR Isuru Ranawaka, Md Taufique Hussain, Charles Block, Gerasimos Gerogiannis, Josep Torrellas, Ariful Azad
2024	J	`jnl`	DynamoLLM: Designing LLM Inference Clusters for Performance and Energy Efficiency. CoRR Jovan Stojkovic, Chaojie Zhang, Íñigo Goiri, Josep Torrellas, Esha Choukse
2024	A*	`conf`	EcoFaaS: Rethinking the Design of Serverless Environments for Energy Efficiency. ISCA Jovan Stojkovic, Nikoleta Iliakopoulou, Tianyin Xu, Hubertus Franke, Josep Torrellas
2024	—	`conf`	Everywhere All at Once: Co-Location Attacks on Public Cloud FaaS. ASPLOS (1) Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas
2024	B	`conf`	FriendlyFoe: Adversarial Machine Learning as a Practical Architectural Defense against Side Channel Attacks. PACT Hyoungwook Nam, Raghavendra Pradyumna Pothukuchi, Bo Li, Nam Sung Kim, Josep Torrellas
2024	A*	`conf`	HADES: Hardware-Assisted Distributed Transactions in the Age of Fast Networks and SmartNICs. ISCA Apostolos Kokolis, Antonis Psistakis, Benjamin Reidys, Jian Huang, Josep Torrellas
2024	A*	`conf`	HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures. HPCA Gerasimos Gerogiannis, Sriram Aananthakrishnan, Josep Torrellas, Ibrahim Hur
2024	J	`jnl`	Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud (Extended Version). CoRR Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas
2024	—	`conf`	Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud. ASPLOS (2) Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas
2024	A*	`conf`	MINOS: Distributed Consistency and Persistency Protocol Implementation & Offloading to SmartNICs. HPCA Antonis Psistakis, Fabien Chaix, Josep Torrellas
2024	A*	`conf`	Mosaic: Harnessing the Micro-Architectural Resources of Servers in Serverless Environments. MICRO Jovan Stojkovic, Esha Choukse, Enrique Saurez, Íñigo Goiri, Josep Torrellas
2024	J	`jnl`	Practical Online Reinforcement Learning for Microprocessors With Micro-Armed Bandit. IEEE Micro Gerasimos Gerogiannis, Josep Torrellas
2024	J	`jnl`	Towards Greener LLMs: Bringing Energy-Efficiency to the Forefront of LLM Inference. CoRR Jovan Stojkovic, Esha Choukse, Chaojie Zhang, Íñigo Goiri, Josep Torrellas
2024	J	`jnl`	Transforming the Hybrid Cloud for Emerging AI Workloads. CoRR Deming Chen, Alaa Youssef, Ruchi Pendse, André Schleife, Bryan K. Clark, Hendrik F. Hamann, Jingrui He, Teodoro Laino, Lav R. Varshney, Yuxiong Wang, Avirup Sil, Reyhaneh Jabbarvand, Tianyin Xu, Volodymyr V. Kindratenko, Carlos H. A. Costa, Sarita V. Adve, Charith Mendis, Minjia Zhang, Santiago Núñez-Corrales, Raghu K. Ganti, Mudhakar Srivatsa, Nam Sung Kim, Josep Torrellas, Jian Huang, Seetharami R. Seelam, Klara Nahrstedt, Tarek F. Abdelzaher, Tamar Eilam, Huimin Zhao, Matteo Manica, Ravishankar K. Iyer, Martin Hirzel, Vikram S. Adve, Darko Marinov, Hubertus Franke, Hanghang Tong, Elizabeth A. Ainsworth, Han Zhao, Deepak Vasisht, Minh Do, Fábio Oliveira, Giovanni Pacifici, Ruchir Puri, Priya Nagpurkar
2024	—	`conf`	Two-Face: Combining Collective and One-Sided Communication for Efficient Distributed SpMM. ASPLOS (2) Charles Block, Gerasimos Gerogiannis, Charith Mendis, Ariful Azad, Josep Torrellas
2023	J	`jnl`	Defensive ML: Defending Architectural Side-channels with Adversarial Obfuscation. CoRR Hyoungwook Nam, Raghavendra Pradyumna Pothukuchi, Bo Li, Nam Sung Kim, Josep Torrellas
2023	J	`jnl`	Input-sensitive dense-sparse primitive compositions for GNN acceleration. CoRR Damitha Lenadora, Vimarsh Sathia, Gerasimos Gerogiannis, Serif Yesil, Josep Torrellas, Charith Mendis
2023	A*	`conf`	MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency. ISCA Jovan Stojkovic, Tianyin Xu, Hubertus Franke, Josep Torrellas
2023	A*	`conf`	Memory-Efficient Hashed Page Tables. HPCA Jovan Stojkovic, Namrata Mantri, Dimitrios Skarlatos, Tianyin Xu, Josep Torrellas
2023	A*	`conf`	Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-Making. MICRO Gerasimos Gerogiannis, Josep Torrellas
2023	A*	`conf`	SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM. ISCA Gerasimos Gerogiannis, Serif Yesil, Damitha Lenadora, Dingyuan Cao, Charith Mendis, Josep Torrellas
2023	A*	`conf`	SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution. HPCA Jovan Stojkovic, Tianyin Xu, Hubertus Franke, Josep Torrellas
2023	—	`conf`	Untangle: A Principled Framework to Design Low-Leakage, High-Performance Dynamic Partitioning Schemes. ASPLOS (3) Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas
2023	B	`conf`	WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning. PPoPP Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas
2023	A*	`conf`	μManycore: A Cloud-Native CPU for Tail at Scale. ISCA Jovan Stojkovic, Chunao Liu, Muhammad Shahbaz, Josep Torrellas
2022	A*	`conf`	Binoculars: Contention-Based Side-Channel Attacks Exploiting the Page Walker. USENIX Security Symposium Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas
2022	A	`conf`	Cloak: tolerating non-volatile cache read latency. ICS Apostolos Kokolis, Namrata Mantri, Shrikanth Ganapathy, Josep Torrellas, John Kalamatianos
2022	A	`conf`	Dense dynamic blocks: optimizing SpMM for processors with vector and matrix units using machine learning techniques. ICS Serif Yesil, José E. Moreira, Josep Torrellas
2022	J	`jnl`	Distributed Data Persistency. IEEE Micro Apostolos Kokolis, Antonis Psistakis, Benjamin Reidys, Jian Huang, Josep Torrellas
2022	A*	`conf`	Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. ISCA Zhangxiaowen Gong, Houxiang Ji, Yao Yao, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas
2022	A*	`conf`	Parallel virtualized memory translation with nested elastic cuckoo page tables. ASPLOS Jovan Stojkovic, Dimitrios Skarlatos, Apostolos Kokolis, Tianyin Xu, Josep Torrellas
2022	A*	`conf`	Pinned loads: taming speculative loads in secure processors. ASPLOS Zirui Neil Zhao, Houxiang Ji, Adam Morrison, Darko Marinov, Josep Torrellas
2022	J	`jnl`	UniHeap: Managing Persistent Objects Across Managed Runtimes for Non-Volatile Memory. CoRR Daixuan Li, Benjamin Reidys, Jinghan Sun, Thomas Shull, Josep Torrellas, Jian Huang
2021	J	`jnl`	A Method for Hiding the Increased Non-Volatile Cache Read Latency. CoRR Apostolos Kokolis, Namrata Mantri, Shrikanth Ganapathy, Josep Torrellas, John Kalamatianos
2021	J	`jnl`	BabelFish: Fusing Address Translations for Containers. IEEE Micro Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, Josep Torrellas
2021	A*	`conf`	Distributed Data Persistency. MICRO Apostolos Kokolis, Antonis Psistakis, Benjamin Reidys, Jian Huang, Josep Torrellas
2021	A*	`conf`	Execution Dependence Extension (EDE): ISA Support for Eliminating Fences. ISCA Thomas Shull, Ilias Vougioukas, Nikos Nikoleris, Wendy Elsasser, Josep Torrellas
2021	A	`conf`	Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores. DATE Antonio Franques, Sergi Abadal, Haitham Hassanieh, Josep Torrellas
2021	A*	`conf`	Jamais vu: thwarting microarchitectural replay attacks. ASPLOS Dimitrios Skarlatos, Zirui Neil Zhao, Riccardo Paccagnella, Christopher W. Fletcher, Josep Torrellas
2021	A*	`conf`	Maya: Using Formal Control to Obfuscate Power Side Channels. ISCA Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Alexander G. Schwing, Josep Torrellas
2021	Misc	`conf`	One Protocol to Rule Them All: Wireless Network-on-Chip using Deep Reinforcement Learning. NSDI Suraj Jog, Zikun Liu, Antonio Franques, Vimuth Fernando, Sergi Abadal, Josep Torrellas, Haitham Hassanieh
2021	A*	`conf`	Speculative interference attacks: breaking invisible speculation schemes. ASPLOS Mohammad Behnia, Prateek Sahu, Riccardo Paccagnella, Jiyong Yu, Zirui Neil Zhao, Xiang Zou, Thomas Unterluggauer, Josep Torrellas, Carlos V. Rozas, Adam Morrison, Frank McKeen, Fangfei Liu, Ron Gabor, Christopher W. Fletcher, Abhishek Basak, Alaa R. Alameldeen
2021	J	`jnl`	Speculative taint tracking (STT): a comprehensive protection for speculatively accessed data. Commun. ACM Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher
2021	Misc	`conf`	UniHeap: managing persistent objects across managed runtimes for non-volatile memory. SYSTOR Daixuan Li, Benjamin Reidys, Jinghan Sun, Thomas Shull, Josep Torrellas, Jian Huang
2021	A*	`conf`	WiDir: A Wireless-Enabled Directory Cache Coherence Protocol. HPCA Antonio Franques, Apostolos Kokolis, Sergi Abadal, Vimuth Fernando, Sasa Misailovic, Josep Torrellas
2020	A*	`conf`	BabelFish: Fusing Address Translations for Containers. ISCA Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, Josep Torrellas
2020	A*	`conf`	Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures. USENIX Security Symposium Mengjia Yan, Christopher W. Fletcher, Josep Torrellas
2020	A*	`conf`	Draco: Architectural and Operating System Support for System Call Security. MICRO Dimitrios Skarlatos, Qingrong Chen, Jianyan Chen, Tianyin Xu, Josep Torrellas
2020	A*	`conf`	Elastic Cuckoo Page Tables: Rethinking Virtual Memory Translation for Parallelism. ASPLOS Dimitrios Skarlatos, Apostolos Kokolis, Tianyin Xu, Josep Torrellas
2020	J	`jnl`	Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication. IEEE Trans. Commun. Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio
2020	J	`jnl`	MicroScope: Enabling Microarchitectural Replay Attacks. IEEE Micro Dimitrios Skarlatos, Mengjia Yan, Bhargava Gopireddy, Read Sprabery, Josep Torrellas, Christopher W. Fletcher
2020	—	`conf`	Millimeter wave wireless network on chip using deep reinforcement learning. SIGCOMM Posters and Demos Suraj Jog, Zikun Liu, Antonio Franques, Vimuth Fernando, Haitham Hassanieh, Sergi Abadal, Josep Torrellas
2020	A*	`conf`	P-INSPECT: Architectural Support for Programmable Non-Volatile Memory Frameworks. MICRO Apostolos Kokolis, Thomas Shull, Jian Huang, Josep Torrellas
2020	A*	`conf`	SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. MICRO Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Sara S. Baghsorkhi, Josep Torrellas
2020	A	`conf`	Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors. ICS Azin Heidarshenas, Tanmay Gangwani, Serif Yesil, Adam Morrison, Josep Torrellas
2020	B	`conf`	SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors. PACT Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas
2020	A*	`conf`	Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis. MICRO Zirui Neil Zhao, Houxiang Ji, Mengjia Yan, Jiyong Yu, Christopher W. Fletcher, Adam Morrison, Darko Marinov, Josep Torrellas
2020	A*	`conf`	Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution. ISCA Jiyong Yu, Namrata Mantri, Josep Torrellas, Adam Morrison, Christopher W. Fletcher
2020	J	`jnl`	Speculative Interference Attacks: Breaking Invisible Speculation Schemes. CoRR Mohammad Behnia, Prateek Sahu, Riccardo Paccagnella, Jiyong Yu, Zirui Neil Zhao, Xiang Zou, Thomas Unterluggauer, Josep Torrellas, Carlos V. Rozas, Adam Morrison, Frank McKeen, Fangfei Liu, Ron Gabor, Christopher W. Fletcher, Abhishek Basak, Alaa R. Alameldeen
2020	J	`jnl`	Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data. IEEE Micro Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher
2020	A	`conf`	Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization. SC Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas
2020	A	`conf`	V-Combiner: speeding-up iterative graph processing on a shared-memory platform with vertex merging. ICS Azin Heidarshenas, Serif Yesil, Dimitrios Skarlatos, Sasa Misailovic, Adam Morrison, Josep Torrellas
2019	A*	`conf`	Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World. IEEE Symposium on Security and Privacy Mengjia Yan, Read Sprabery, Bhargava Gopireddy, Christopher W. Fletcher, Roy H. Campbell, Josep Torrellas
2019	A*	`conf`	AutoPersist: an easy-to-use Java NVM framework based on reachability. PLDI Thomas Shull, Jian Huang, Josep Torrellas
2019	A*	`conf`	Designing vertical processors in monolithic 3D. ISCA Bhargava Gopireddy, Josep Torrellas
2019	J	`jnl`	Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication. CoRR Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio
2019	A*	`conf`	InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (Corrigendum). MICRO Mengjia Yan, Jiho Choi, Dimitrios Skarlatos, Adam Morrison, Christopher W. Fletcher, Josep Torrellas
2019	J	`jnl`	Maya: Falsifying Power Sidechannels with Operating System Support. CoRR Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas
2019	A*	`conf`	MicroScope: enabling microarchitectural replay attacks. ISCA Dimitrios Skarlatos, Mengjia Yan, Bhargava Gopireddy, Read Sprabery, Josep Torrellas, Christopher W. Fletcher
2019	A*	`conf`	NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory. HPCA Thomas Shull, Jiho Choi, María Jesús Garzarán, Josep Torrellas
2019	C	`conf`	Opportunistic Beamforming in Wireless Network-on-Chip. ISCAS Sergi Abadal, Adrián Marruedo, Antonio Franques, Hamidreza Taghvaee, Albert Cabellos-Aparicio, Jin Zhou, Josep Torrellas, Eduard Alarcón
2019	J	`jnl`	Opportunistic Beamforming in Wireless Network-on-Chip. CoRR Sergi Abadal, Adrián Marruedo, Antonio Franques, Hamidreza Taghvaee, Albert Cabellos-Aparicio, Jin Zhou, Josep Torrellas, Eduard Alarcón
2019	A*	`conf`	PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems. HPCA Apostolos Kokolis, Dimitrios Skarlatos, Josep Torrellas
2019	B	`conf`	QuickCheck: using speculation to reduce the overhead of checks in NVM frameworks. VEE Thomas Shull, Jian Huang, Josep Torrellas
2019	A*	`conf`	Replica: A Wireless Manycore for Communication-Intensive and Approximate Data. ASPLOS Vimuth Fernando, Antonio Franques, Sergi Abadal, Sasa Misailovic, Josep Torrellas
2019	A*	`conf`	Reusable inline caching for JavaScript performance. PLDI Jiho Choi, Thomas Shull, Josep Torrellas
2019	A*	`conf`	SecDir: a secure directory to defeat directory side-channel attacks. ISCA Mengjia Yan, Jen-Yang Wen, Christopher W. Fletcher, Josep Torrellas
2019	J	`jnl`	SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors. CoRR Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas
2019	A*	`conf`	Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data. MICRO Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher
2019	A*	`conf`	Tangram: Integrated Control of Heterogeneous Computers. MICRO Raghavendra Pradyumna Pothukuchi, Joseph L. Greathouse, Karthik Rao, Christopher Erb, Leonardo Piga, Petros G. Voulgaris, Josep Torrellas
2019	A	`conf`	Understanding priority-based scheduling of graph algorithms on a shared-memory platform. SC Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas
2018	J	`jnl`	An empirical study of the effect of source-level loop transformations on compiler stability. Proc. ACM Program. Lang. Zhangxiaowen Gong, Zhi Chen, Justin Josef Szaday, David C. Wong, Zehra Sura, Neftali Watkinson, Saeed Maleki, David A. Padua, Alexander V. Veidenbaum, Alexandru Nicolau, Josep Torrellas
2018	B	`conf`	Biased reference counting: minimizing atomic operations in garbage collection. PACT Jiho Choi, Thomas Shull, Josep Torrellas
2018	J	`jnl`	Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures. CoRR Mengjia Yan, Christopher W. Fletcher, Josep Torrellas
2018	—	`conf`	Defining a high-level programming model for emerging NVRAM technologies. ManLang Thomas Shull, Jian Huang, Josep Torrellas
2018	A*	`conf`	HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs. ISCA Bhargava Gopireddy, Dimitrios Skarlatos, Wenjuan Zhu, Josep Torrellas
2018	A*	`conf`	InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy. MICRO Mengjia Yan, Jiho Choi, Dimitrios Skarlatos, Adam Morrison, Christopher W. Fletcher, Josep Torrellas
2018	J	`jnl`	Medium Access Control in Wireless Network-on-Chip: A Context Analysis. IEEE Commun. Mag. Sergi Abadal, Albert Mestres, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio
2018	J	`jnl`	Medium Access Control in Wireless Network-on-Chip: A Context Analysis. CoRR Sergi Abadal, Albert Mestres, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio
2018	C	`conf`	Millimeter-Wave Propagation within a Computer Chip Package. ISCAS Xavier Timoneda, Sergi Abadal, Albert Cabellos-Aparicio, Dionysios Manessis, Jin Zhou, Antonio Franques, Josep Torrellas, Eduard Alarcón
2018	J	`jnl`	Millimeter-Wave Propagation within a Computer Chip Package. CoRR Xavier Timoneda, Sergi Abadal, Albert Cabellos-Aparicio, Dionysios Manessis, Jin Zhou, Antonio Franques, Josep Torrellas, Eduard Alarcón
2018	J	`jnl`	OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture. IEEE Trans. Parallel Distributed Syst. Sergi Abadal, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio
2018	A*	`conf`	Record-Replay Architecture as a General Security Framework. HPCA Yasser Shalabi, Mengjia Yan, Nima Honarmand, Ruby B. Lee, Josep Torrellas
2018	—	`conf`	Structured Singular Value Control for Modular Resource Management in Multilayer Computers. CDC Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas
2018	A*	`conf`	Yukta: Multilayer Resource Controllers to Maximize Efficiency. ISCA Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas
2017	—	`conf`	LORE: A loop repository for the evaluation of compilers. IISWC Zhi Chen, Zhangxiaowen Gong, Justin Josef Szaday, David C. Wong, David A. Padua, Alexandru Nicolau, Alexander V. Veidenbaum, Neftali Watkinson, Zehra Sura, Saeed Maleki, Josep Torrellas, Gerald DeJong
2017	B	`conf`	Multilayer Compute Resource Management with Robust Control Theory. PACT Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas
2017	A*	`conf`	Pageforge: a near-memory content-aware page-merging architecture. MICRO Dimitrios Skarlatos, Nam Sung Kim, Josep Torrellas
2017	A*	`conf`	Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks. ISCA Mengjia Yan, Bhargava Gopireddy, Thomas Shull, Josep Torrellas
2017	A*	`conf`	ShortCut: Architectural Support for Fast Object Access in Scripting Languages. ISCA Jiho Choi, Thomas Shull, María Jesús Garzarán, Josep Torrellas
2017	B	`conf`	Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency. PACT Raghavendra Pradyumna Pothukuchi, Amin Ansari, Bhargava Gopireddy, Josep Torrellas
2017	J	`jnl`	Survive: Pointer-Based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery. IEEE Comput. Archit. Lett. Amirhossein Mirhosseini, Aditya Agrawal, Josep Torrellas
2017	A*	`conf`	Xylem: enhancing vertical thermal conduction in 3D processor-memory stacks. MICRO Aditya Agrawal, Josep Torrellas, Sachin Idgunji
2016	J	`jnl`	21st Century Computer Architecture. CoRR Mark D. Hill, Sarita V. Adve, Luis Ceze, Mary Jane Irwin, David R. Kaeli, Margaret Martonosi, Josep Torrellas, Thomas F. Wenisch, David A. Wood, Katherine A. Yelick
2016	—	`conf`	A MAC protocol for Reliable Broadcast Communications in Wireless Network-on-Chip. NoCArc@MICRO Albert Mestres, Sergi Abadal, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio
2016	A	`conf`	Architecting and Programming a Hardware-Incoherent Multiprocessor Cache Hierarchy. IPDPS Wooil Kim, Sanket Tavarageri, P. Sadayappan, Josep Torrellas
2016	A*	`conf`	CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization. ASPLOS Tanmay Gangwani, Adam Morrison, Josep Torrellas
2016	Misc	`conf`	Compiler Support for Software Cache Coherence. HiPC Sanket Tavarageri, Wooil Kim, Josep Torrellas, P. Sadayappan
2016	—	`ch.`	Many-Core Architecture for NTC: Energy Efficiency from the Ground Up. Near Threshold Computing Josep Torrellas
2016	A*	`conf`	ReplayConfusion: Detecting cache-based covert channel attacks using record and replay. MICRO Mengjia Yan, Yasser Shalabi, Josep Torrellas
2016	A*	`conf`	SCsafe: Logging sequential consistency violations continuously and precisely. HPCA Yuelu Duan, David A. Koufaty, Josep Torrellas
2016	A*	`conf`	ScalCore: Designing a core for voltage scalability. HPCA Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, Asit K. Mishra
2016	A*	`conf`	Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. MICRO Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas
2016	Misc	`conf`	Toward Extreme-Scale Processor Chips. HiPC Josep Torrellas
2016	A*	`conf`	Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures. ISCA Raghavendra Pradyumna Pothukuchi, Amin Ansari, Petros G. Voulgaris, Josep Torrellas
2016	B	`conf`	WearCore: A Core for Wearable Workloads. PACT Sanyam Mehta, Josep Torrellas
2016	A*	`conf`	WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication. ASPLOS Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Josep Torrellas
2015	A*	`conf`	Asymmetric Memory Fences: Optimizing Both Performance and Implementability. ASPLOS Yuelu Duan, Nima Honarmand, Josep Torrellas
2014	A*	`conf`	Dynamically detecting and tolerating IF-Condition Data Races. HPCA Shanxiang Qi, Abdullah Muzahid, Wonsun Ahn, Josep Torrellas
2014	A	`conf`	Extreme-scale computer architecture: Energy efficiency from the ground up DATE Josep Torrellas
2014	A*	`conf`	Improving JavaScript performance by deconstructing the type system. PLDI Wonsun Ahn, Jiho Choi, Thomas Shull, María Jesús Garzarán, Josep Torrellas
2014	B	`ed.`	International Conference on Parallel Architectures and Compilation, PACT '14, Edmonton, AB, Canada, August 24-27, 2014 PACT José Nelson Amaral, Josep Torrellas
2014	A*	`conf`	Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules. HPCA Aditya Agrawal, Amin Ansari, Josep Torrellas
2014	A*	`conf`	OmniOrder: Directory-based conflict serialization of transactions. ISCA Xuehai Qian, Benjamín Sahelices, Josep Torrellas
2014	A*	`conf`	RelaxReplay: record and replay for relaxed-consistency multiprocessors. ASPLOS Nima Honarmand, Josep Torrellas
2014	A*	`conf`	Replay debugging: Leveraging record and replay for program debugging. ISCA Nima Honarmand, Josep Torrellas
2014	A*	`conf`	Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks. HPCA Amin Ansari, Asit K. Mishra, Jianping Xu, Josep Torrellas
2014	A	`conf`	Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy. SC Ehsan Totoni, Josep Torrellas, Laxmikant V. Kalé
2013	A*	`conf`	BulkCommit: scalable and fast commit of atomic blocks in a lazy multiprocessor environment. MICRO Xuehai Qian, Josep Torrellas, Benjamín Sahelices, Depei Qian
2013	J	`jnl`	Coping with Parametric Variation at Near-Threshold Voltages. IEEE Micro Ulya R. Karpuzcu, Nam Sung Kim, Josep Torrellas
2013	A*	`conf`	Cyrus: unintrusive application-level record-replay for replay parallelism. ASPLOS Nima Honarmand, Nathan Dautenhahn, Josep Torrellas, Samuel T. King, Gilles Pokam, Cristiano Pereira
2013	A*	`conf`	DeAliaser: alias speculation using atomic region support. ASPLOS Wonsun Ahn, Yuelu Duan, Josep Torrellas
2013	A*	`conf`	EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing. HPCA Ulya R. Karpuzcu, Abhishek A. Sinkar, Nam Sung Kim, Josep Torrellas
2013	—	`conf`	Extreme scale computer architecture: Energy efficiency from the ground up. ASAP Josep Torrellas
2013	A*	`conf`	Illusionist: Transforming lightweight cores into aggressive cores on demand. HPCA Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, Scott A. Mahlke
2013	A*	`conf`	QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs. ISCA Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, Justin Emile Gottschlich, Nima Honarmand, Nathan Dautenhahn, Samuel T. King, Josep Torrellas
2013	A*	`conf`	Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. HPCA Aditya Agrawal, Prabhat Jain, Amin Ansari, Josep Torrellas
2013	A*	`conf`	Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu
2013	A*	`conf`	Volition: scalable and precise sequential consistency violation detection. ASPLOS Xuehai Qian, Josep Torrellas, Benjamín Sahelices, Depei Qian
2013	A*	`conf`	WeeFence: toward making fences free in TSO. ISCA Yuelu Duan, Abdullah Muzahid, Josep Torrellas
2012	J	`jnl`	2012 International Symposium on Computer Architecture Influential Paper Award. IEEE Micro Josep Torrellas
2012	A*	`conf`	BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks. HPCA Yuelu Duan, Xing Zhou, Wonsun Ahn, Josep Torrellas
2012	A*	`conf`	BulkSMT: Designing SMT processors for atomic-block execution. HPCA Xuehai Qian, Benjamín Sahelices, Josep Torrellas
2012	B	`conf`	Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs. ISPASS Ehsan Totoni, Babak Behzad, Swapnil Ghike, Josep Torrellas
2012	C	`conf`	FlexRAM: Toward an advanced Intelligent Memory system. ICCD Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Pratap Pattnaik, Josep Torrellas
2012	C	`conf`	FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper. ICCD Josep Torrellas
2012	A*	`conf`	Pacman: Tolerating asymmetric data races with unintrusive hardware. HPCA Shanxiang Qi, Norimasa Otsuki, Lois Orosa Nogueira, Abdullah Muzahid, Josep Torrellas
2012	A	`conf`	VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages. DSN Ulya R. Karpuzcu, Krishna B. Kolluru, Nam Sung Kim, Josep Torrellas
2012	A*	`conf`	Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically. MICRO Abdullah Muzahid, Shanxiang Qi, Josep Torrellas
2011	—	`ch.`	Cache-Only Memory Architecture (COMA). Encyclopedia of Parallel Computing Josep Torrellas
2011	A*	`conf`	FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes. ISCA Rishi Agarwal, Josep Torrellas
2011	A*	`conf`	Rebound: scalable checkpointing for coherent shared memory. ISCA Rishi Agarwal, Pranav Garg, Josep Torrellas
2011	—	`ch.`	Speculation, Thread-Level. Encyclopedia of Parallel Computing Josep Torrellas
2010	A*	`conf`	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection. MICRO Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas
2010	A*	`conf`	Extreme scale computing: Challenges and opportunities. HPCA Josep Torrellas, Bill Gropp, Vivek Sarkar, Jaime H. Moreno, Kunle Olukotun
2010	B	`conf`	Extreme scale computing: challenges and opportunities. PPoPP Josep Torrellas, Bill Gropp, Jaime H. Moreno, Kunle Olukotun, Vivek Sarkar
2010	A*	`conf`	InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing. MICRO Adrian Nistor, Darko Marinov, Josep Torrellas
2010	A*	`conf`	LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores. HPCA Brian Greskamp, Ulya R. Karpuzcu, Josep Torrellas
2010	A*	`conf`	ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment. MICRO Xuehai Qian, Wonsun Ahn, Josep Torrellas
2009	J	`jnl`	Architectures for Extreme-Scale Computing. Computer Josep Torrellas
2009	A*	`conf`	Blueshift: Designing processors for timing speculation from the ground up. HPCA Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles
2009	A*	`conf`	BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support. MICRO Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, Jae-Woo Lee, Xing Fang, Samuel P. Midkiff, David C. Wong
2009	A*	`conf`	Capo: a software-hardware interface for practical deterministic multiprocessor replay. ASPLOS Pablo Montesinos, Matthew Hicks, Samuel T. King, Josep Torrellas
2009	A	`conf`	How to build a useful thousand-core manycore system? IPDPS Josep Torrellas
2009	A*	`conf`	Light64: lightweight hardware support for data race detection during systematic testing of parallel programs. MICRO Adrian Nistor, Darko Marinov, Josep Torrellas
2009	A*	`conf`	SigRace: signature-based data race detection. ISCA Abdullah Muzahid, Darío Suárez Gracia, Shanxiang Qi, Josep Torrellas
2009	J	`jnl`	SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization. IEEE Micro James Tuck, Wonsun Ahn, Josep Torrellas, Luis Ceze
2009	A*	`conf`	The BubbleWrap many-core: popping cores for sequential acceleration. MICRO Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
2009	J	`jnl`	The Bulk Multicore architecture for improved programmability. Commun. ACM Josep Torrellas, Luis Ceze, James Tuck, Calin Cascaval, Pablo Montesinos, Wonsun Ahn, Milos Prvulovic
2009	J	`jnl`	Two hardware-based approaches for deterministic multiprocessor replay. Commun. ACM Derek Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, Josep Torrellas
2008	—	`conf`	Concurrency control with data coloring. MSPC Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, Josep Torrellas
2008	A*	`conf`	DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently. ISCA Pablo Montesinos, Luis Ceze, Josep Torrellas
2008	A*	`conf`	EVAL: Utilizing processors with variation-induced timing errors. MICRO Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas
2008	A*	`conf`	Facelift: Hiding and slowing down aging in multicores. MICRO Abhishek Tiwari, Josep Torrellas
2008	A*	`conf`	SoftSig: software-exposed hardware signatures for code analysis and optimization. ASPLOS James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
2008	A*	`conf`	Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. ISCA Radu Teodorescu, Josep Torrellas
2007	—	`conf`	A Model for Timing Errors in Processors with Parameter Variation. ISQED Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
2007	A*	`conf`	BulkSC: bulk enforcement of sequential consistency. ISCA Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas
2007	C	`conf`	CAP: Criticality analysis for power-efficient speculative multithreading. ICCD James Tuck, Wei Liu, Josep Torrellas
2007	A*	`conf`	Colorama: Architectural Support for Data-Centric Synchronization. HPCA Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas
2007	C	`conf`	Estimating design time for system circuits. VLSI-SoC Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau
2007	A*	`conf`	Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. MICRO Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas
2007	B	`conf`	Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking. PACT Brian Greskamp, Josep Torrellas
2007	J	`jnl`	Patching Processor Design Errors with Programmable Hardware. IEEE Micro Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas
2007	A*	`conf`	ReCycle: : pipeline adaptation to tolerate process variation. ISCA Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas
2007	C	`conf`	Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates. ISCAS Brian Greskamp, Smruti R. Sarangi, Josep Torrellas
2007	A*	`conf`	Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. MICRO Karin Strauss, Xiaowei Shen, Josep Torrellas
2007	A	`conf`	Using Register Lifetime Predictions to Protect Register Files against Soft Errors. DSN Pablo Montesinos, Wei Liu, Josep Torrellas
2006	—	`conf`	Accurate and efficient filtering for the Intel thread checker race detector. ASID Paul Sack, Brian E. Bliss, Zhiqiang Ma, Paul Petersen, Josep Torrellas
2006	A*	`conf`	Bulk Disambiguation of Speculative Threads in Multiprocessors. ISCA Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval
2006	A	`conf`	CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging. DSN Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
2006	J	`jnl`	CAVA: Using checkpoint-assisted value prediction to hide L2 misses. ACM Trans. Archit. Code Optim. Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau
2006	J	`jnl`	Energy-Efficient Thread-Level Speculation. IEEE Micro Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
2006	A*	`conf`	Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors. ISCA Karin Strauss, Xiaowei Shen, Josep Torrellas
2006	J	`jnl`	Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. IEEE Micro Josep Torrellas
2006	B	`conf`	POSH: a TLS compiler that exploits program structure. PPoPP Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas
2006	A*	`conf`	PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection. MICRO Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas
2006	A*	`conf`	Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware. MICRO Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas
2006	—	`ed.`	Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID 2006, San Jose, California, USA, October 21, 2006 ASID Josep Torrellas
2006	B	`ed.`	Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2006, New York, New York, USA, March 29-31, 2006 PPoPP Josep Torrellas, Siddhartha Chatterjee
2006	A*	`conf`	ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers. HPCA Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, Josep Torrellas
2006	J	`jnl`	SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback. IEEE Micro Radu Teodorescu, Jun Nakano, Josep Torrellas
2006	A*	`conf`	Scalable Cache Miss Handling for High Memory-Level Parallelism. MICRO James Tuck, Luis Ceze, Josep Torrellas
2005	J	`jnl`	Efficient and flexible architectural support for dynamic monitoring. ACM Trans. Archit. Code Optim. Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, Josep Torrellas
2005	Misc	`conf`	Prototyping Architectural Support for Program Rollback Using FPGAs. FCCM Radu Teodorescu, Josep Torrellas
2005	A	`conf`	Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. ICS Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas
2005	A	`conf`	Thread-Level Speculation on a CMP can be energy efficient. ICS Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
2005	J	`jnl`	Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. ACM Trans. Archit. Code Optim. María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
2004	A*	`conf`	AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants. MICRO Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas
2004	J	`jnl`	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction. IEEE Comput. Archit. Lett. Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas
2004	A*	`conf`	iWatcher: Efficient Architectural Support for Software Debugging. ISCA Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas
2004	J	`jnl`	iWatcher: Simple, General Architectural Support for Software Debugging. IEEE Micro Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas
2003	J	`jnl`	Correlation Prefetching with a User-Level Memory Thread. IEEE Trans. Parallel Distributed Syst. Yan Solihin, Jaejin Lee, Josep Torrellas
2003	—	`conf`	Design Trade-Offs in High-Throughput Coherence Controllers. IEEE PACT Anthony-Trung Nguyen, Josep Torrellas
2003	A*	`conf`	Positional Adaptation of Processors: Application to Energy Reduction. ISCA Michael C. Huang, Jose Renau, Josep Torrellas
2003	B	`conf`	Programming the FlexRAM parallel intelligent memory system. PPoPP Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas
2003	A*	`conf`	ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. ISCA Milos Prvulovic, Josep Torrellas
2003	J	`jnl`	Speculative Synchronization: Programmability and Performance for Parallel Codes. IEEE Micro José F. Martínez, Josep Torrellas
2003	A*	`conf`	Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
2003	—	`conf`	Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas
2002	A*	`conf`	Cherry: checkpointed early resource recycling in out-of-order microprocessors. MICRO José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas
2002	A	`conf`	Energy-efficient hybrid wakeup logic. ISLPED Michael C. Huang, Jose Renau, Josep Torrellas
2002	A*	`conf`	ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. ISCA Milos Prvulovic, Josep Torrellas, Zheng Zhang
2002	A	`conf`	SmartApps: An Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction Operations. IPDPS Francis H. Dang, María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Alin Jula, Hao Yu, Nancy M. Amato, Lawrence Rauchwerger, Josep Torrellas
2002	J	`jnl`	Software Trace Cache for Commercial Applications. Int. J. Parallel Program. Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas
2002	A*	`conf`	Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors. HPCA Marcelo H. Cintra, Josep Torrellas
2002	A*	`conf`	Speculative synchronization: applying thread-level speculation to explicitly parallel applications. ASPLOS José F. Martínez, Josep Torrellas
2002	A*	`conf`	Using a User-Level Memory Thread for Correlation Prefetching. ISCA Yan Solihin, Josep Torrellas, Jaejin Lee
2001	—	`conf`	Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors. IEEE PACT María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Josep Torrellas, Alin Jula, Hao Yu, Lawrence Rauchwerger
2001	J	`jnl`	Automatic Code Mapping on an Intelligent Memory Architecture. IEEE Trans. Computers Yan Solihin, Jaejin Lee, Josep Torrellas
2001	A*	`conf`	Automatically Mapping Code on an Intelligent Memory Architecture. HPCA Jaejin Lee, Yan Solihin, Josep Torrellas
2001	A	`conf`	L1 data cache decomposition for energy efficiency. ISLPED Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
2001	A*	`conf`	Removing architectural bottlenecks to the scalability of speculative parallelization. ISCA Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, Josep Torrellas
2001	J	`jnl`	The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. J. Instr. Level Parallelism Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
2001	J	`jnl`	The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. Int. J. Parallel Program. Venkata Krishnan, Josep Torrellas
2000	A*	`conf`	A framework for dynamic energy efficiency and temperature management. MICRO Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
2000	—	`conf`	Adaptively Mapping Code in an Intelligent Memory Architecture. Intelligent Memory Systems Yan Solihin, Jaejin Lee, Josep Torrellas
2000	A*	`conf`	Architectural support for scalable speculative parallelization in shared-memory multiprocessors. ISCA Marcelo H. Cintra, José F. Martínez, Josep Torrellas
2000	—	`conf`	Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Intelligent Memory Systems Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
2000	—	`conf`	SmartApps: An Application Centric Approach to High Performance Computing. LCPC Lawrence Rauchwerger, Nancy M. Amato, Josep Torrellas
2000	A*	`conf`	Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. HPCA Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen
2000	C	`conf`	Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. ICCD Qiang Cao, Josep Torrellas, H. V. Jagadish
1999	J	`jnl`	A Chip-Multiprocessor Architecture with Speculative Multithreading. IEEE Trans. Computers Venkata Krishnan, Josep Torrellas
1999	C	`conf`	Cache Optimization for Memory-Resident Decision Support Commercial Workloads. ICCD Pedro Trancoso, Josep Torrellas
1999	J	`jnl`	Cache-Only Memory Architectures. Computer Fredrik Dahlgren, Josep Torrellas
1999	B	`conf`	Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors. ICPP David A. Koufaty, Josep Torrellas
1999	J	`jnl`	Comprehensive Hardware and Software Support for Operating Systems to Exploit. IEEE Trans. Computers Chun Xia, Josep Torrellas
1999	C	`conf`	Detailed Characterization of a Quad Pentium Pro Server Running TPC-D. ICCD Qiang Cao, Josep Torrellas, Pedro Trancoso, Josep Lluís Larriba-Pey, Bob Knighten, Youjip Won
1999	J	`jnl`	Excel-NUMA: Toward Programmability, Simplicity, and High Performance. IEEE Trans. Computers Zheng Zhang, Marcelo H. Cintra, Josep Torrellas
1999	C	`conf`	FlexRAM: Toward an Advanced Intelligent Memory System. ICCD Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik
1999	A*	`conf`	Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. HPCA Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
1999	A	`conf`	Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity. International Conference on Supercomputing José F. Martínez, Josep Torrellas, José Duato
1999	B	`conf`	Optimization of Instruction Fetch for Decision Support Workloads. ICPP Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas
1999	A	`conf`	Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors. SC Josep Torrellas, Yan Solihin, Vinh Vi Lam
1999	A*	`conf`	Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. HPCA Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas
1999	A	`conf`	Software trace cache. International Conference on Supercomputing Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero
1999	—	`conf`	The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. IEEE PACT Venkata Krishnan, Josep Torrellas
1999	—	`conf`	Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability. PP Josep Torrellas
1998	—	`conf`	A Clustered Approach to Multithreaded Processors. IPPS/SPDP Venkata Krishnan, Josep Torrellas
1998	—	`conf`	An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors. IEEE PACT Venkata Krishnan, Josep Torrellas
1998	B	`conf`	An IRAM architecture for image analysis and pattern recognition. ICPR Yi Kang, Josep Torrellas, Thomas S. Huang
1998	A	`conf`	Comparing Data Forwarding and Prefetching for Communication-induced Misses in Shared-memory MPs. International Conference on Supercomputing David A. Koufaty, Josep Torrellas
1998	—	`conf`	Computer architecture education at the University of Illinois. WCAE@ISCA Josep Torrellas
1998	A*	`conf`	Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma. HPCA Sujoy Basu, Josep Torrellas
1998	A	`conf`	Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-multiprocessor. International Conference on Supercomputing Venkata Krishnan, Josep Torrellas
1998	A*	`conf`	Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors. HPCA Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
1998	J	`jnl`	Optimizing the Instruction Cache Performance of the Operating System. IEEE Trans. Computers Josep Torrellas, Chun Xia, Russell L. Daigle
1998	—	`conf`	Use IRAM for Rasterization. ICIP (3) Yi Kang, Josep Torrellas, Thomas S. Huang
1997	A*	`conf`	Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA. HPCA Zheng Zhang, Josep Torrellas
1997	A*	`conf`	Speeding up the Memory Hierarchy in Flat COMA Multiprocessors. HPCA Liuxi Yang, Josep Torrellas
1997	A*	`conf`	The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors. HPCA Pedro Trancoso, Josep Lluís Larriba-Pey, Zheng Zhang, Josep Torrellas
1997	J	`jnl`	The Performance of the Cedar Multistage Switching Network. IEEE Trans. Parallel Distributed Syst. Josep Torrellas, Zheng Zhang
1996	—	`conf`	An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors. SPDP Manuel P. Malumbres, José Duato, Josep Torrellas
1996	—	`conf`	Computer architecture education at the University of Illinois: current status and some thoughts. WCAE@HPCA Josep Torrellas
1996	J	`jnl`	Data Forwarding in Scalable Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. David A. Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas
1996	A*	`conf`	Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors. HPCA Alain Raynaud, Zheng Zhang, Josep Torrellas
1996	A*	`conf`	Improving the Data Cache Performance of Multiprocessor Operating Systems. HPCA Chun Xia, Josep Torrellas
1996	A*	`conf`	Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses. ISCA Chun Xia, Josep Torrellas
1996	A	`conf`	Optimizing Primary Data Caches for Parallel Scientific Applications: The Pool Buffer Approach. International Conference on Supercomputing Liuxi Yang, Josep Torrellas
1996	C	`conf`	The Augmint multiprocessor simulation toolkit for Intel x86 architectures. ICCD Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas
1996	—	`conf`	The Impact of Speeding up Critical Sections with Data Prefetching and Forwarding. ICPP, Vol. 3 Pedro Trancoso, Josep Torrellas
1995	A	`conf`	Data Forwarding in Scalable Shared-Memory Multiprocessors. International Conference on Supercomputing David A. Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas
1995	J	`jnl`	Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors. J. Parallel Distributed Comput. Josep Torrellas, Andrew Tucker, Anoop Gupta
1995	A*	`conf`	Optimizing Instruction Cache Performance for Operating System Intensive Workloads. HPCA Josep Torrellas, Chun Xia, Russell L. Daigle
1995	A*	`conf`	Speeding Up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching. ISCA Zheng Zhang, Josep Torrellas
1994	A	`conf`	An efficient algorithm for the run-time parallelization of DOACROSS loops. SC Ding-Kai Chen, Josep Torrellas, Pen-Chung Yew
1994	—	`conf`	Comparing the Performance of the DASH and CEDAR Multiprocessors. ICPP (2) Josep Torrellas, David A. Koufaty, David A. Padua
1994	J	`jnl`	False Sharing ans Spatial Locality in Multiprocessor Caches. IEEE Trans. Computers Josep Torrellas, Monica S. Lam, John L. Hennessy
1994	A	`conf`	The performance of the Cedar multistage switching network. SC Josep Torrellas, Zheng Zhang
1993	A*	`conf`	Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors: A Summary. SIGMETRICS Josep Torrellas, Andrew Tucker, Anoop Gupta
1992	A*	`conf`	Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System. ASPLOS Josep Torrellas, Anoop Gupta, John L. Hennessy
1990	A*	`conf`	Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared Memory Multiprocessor. SIGMETRICS Josep Torrellas, John L. Hennessy, Thierry Weil
1990	—	`conf`	Estimating the Performance Advantages of Relaxing Consistency in a Shared Memory Multiprocessor. ICPP (1) Josep Torrellas, John L. Hennessy
1990	—	`conf`	Share Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates. ICPP (2) Josep Torrellas, Monica S. Lam, John L. Hennessy