Josef Strnadel

38 papers A 3C 19Journal 4Unranked 12
YearRankTypeTitle / Venue / Authors
2025 A conf
Multi-Partner Project: LoLiPoP-IoT - Design and Simulation of Energy-Efficient Devices for the Internet of Things.
DATE
Jakub Lojda, Josef Strnadel, Pavel Smrz, Václav Simek
2025 C conf
Portable Simulation Models for Energy Aspects of IoT Devices in the LoLiPoP-IoT Project.
DSD
Jakub Lojda, Daire Joyce, Pavel Smrz, Shruti Kathuria, Josef Strnadel, Caitlin Quinn, Václav Simek, Patrik Staron
2024 — conf
First Steps Towards Unified Low-Power IoT Design: The "DYNAMIC" Framework.
EWDTS
Jakub Lojda, Josef Strnadel, Pavel Smrz, Václav Simek
2024 — conf
On SMC-Based Dependability Analysis in LoLiPoP-IoT Project.
AISoLA
Josef Strnadel, Jakub Lojda, Pavel Smrz, Václav Simek
2024 C conf
The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things.
DSD
Jakub Lojda, Josef Strnadel, Václav Simek, Pavel Smrz, Mike Hayes, Ralf Popp
2024 — conf
Using Statistical Model Checker for Schedulability Analysis of Real-Time Systems Under Uncertainty.
AISoLA
Josef Strnadel
2022 C conf
Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking.
DDECS
Josef Strnadel
2021 C conf
Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults.
DDECS
Josef Strnadel
2020 A conf
Statistical Model Checking of Approximate Circuits: Challenges and Opportunities.
DATE
Josef Strnadel
2019 A conf
Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates.
DATE
Josef Strnadel
2018 J jnl
Predictability Analysis of Interruptible Systems by Statistical Model Checking.
IEEE Des. Test
Josef Strnadel
2018 — conf
Statistical Model Checking of Processor Systems in Various Interrupt Scenarios.
ISoLA (2)
Josef Strnadel
2017 C conf
On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking.
DSD
Josef Strnadel
2016 — conf
On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle.
ISoLA (1)
Josef Strnadel
2015 — conf
Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads.
ECBS-EERC
Josef Strnadel
2014 C conf
Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework.
DSD
Josef Strnadel, Martin Pokorny
2014 J jnl
Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems.
Comput. Informatics
Josef Strnadel, Frantisek Slimarik
2013 — conf
Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates.
ARCS
Josef Strnadel
2013 C conf
On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems.
DDECS
Josef Strnadel
2012 C conf
Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems.
DDECS
Josef Strnadel
2012 C conf
On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels.
DSD
Josef Strnadel, Frantisek Slimarik
2011 C conf
On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits.
DSD
Michal Rumplík, Josef Strnadel
2010 C conf
Reduction of power dissipation through parallel optimization of test vector and scan register sequences.
DDECS
Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
2010 C conf
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption.
DSD
Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
2010 — conf
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application.
ICES
Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel
2008 J jnl
Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits.
Comput. Informatics
Josef Strnadel, Tomas Pecenka, Zdenek Kotásek
2008 C conf
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path.
DSD
Josef Strnadel
2007 C conf
Test Controller Synthesis Constrained by Circuit Testability Analysis.
DSD
Richard Ruzicka, Josef Strnadel
2006 — conf
Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules.
ECBS
Josef Strnadel, Arghya Kumar Dhali
2006 C conf
Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space.
DDECS
Josef Strnadel
2006 — conf
SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System.
ECBS
Josef Strnadel, Zdenek Kotásek
2006 J jnl
Testability Analysis and Improvements of Register-Transfer Level Digital Circuits.
Comput. Artif. Intell.
Josef Strnadel
2006 C conf
Testability Estimation Based on Controllability and Observability Parameters.
DSD
Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina
2005 — conf
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties.
Evolvable Hardware
Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel
2005 C conf
Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies.
DSD
Josef Strnadel, Zdenek Kotásek
2004 — conf
The Identification of registers in RTL Structures for the Test Application.
ISoLA (Preliminary proceedings)
Daniel Mika, Josef Strnadel, Zdenek Kotásek
2003 C conf
Test scheduling for embedded systems.
DSD
Zdenek Kotásek, Daniel Mika, Josef Strnadel
2002 C conf
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level.
DSD
Josef Strnadel, Zdenek Kotásek