Jose Renau - RankMe

66 papers A* 15A 10B 8C 6Journal 15Unranked 10

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Aligning Netlist to Source Code using SynAlign. CoRR Sakshi Garg, Jose Renau
2025	—	`conf`	Beyond Verilog: Agents for Emerging HDLs. COINS Farzaneh Rabiei Kashanaki, Mark Zakharov, Jose Renau
2025	J	`jnl`	Enabling New HDLs with Agents. CoRR Mark Zakharov, Farzaneh Rabiei Kashanaki, Jose Renau
2023	B	`conf`	A Multi-threaded Fast Hardware Compiler for HDLs. CC Sheng-Hong Wang, Hunter James Coffman, Kenneth Mayer, Sakshi Garg, Jose Renau
2021	—	`conf`	Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. HCS David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau
2021	A*	`conf`	Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation. MICRO Nursultan Kabylkas, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, Jose Renau
2020	J	`jnl`	LiveHD: A Productive Live Hardware Development Flow. IEEE Micro Sheng-Hong Wang, Rafael Trapani Possignolo, Haven Blake Skinner, Jose Renau
2020	B	`conf`	LiveSim: A Fast Hot Reload Simulator for HDLs. ISPASS Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau
2020	J	`jnl`	Load Driven Branch Predictor (LDBP). CoRR Akash Sridhar, Nursultan Kabylkas, Jose Renau
2019	A*	`conf`	EMI Architectural Model and Core Hopping. MICRO Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau
2019	A*	`conf`	SMatch: Structural Matching for Fast Resynthesis in FPGAs. DAC Rafael Trapani Possignolo, Jose Renau
2018	—	`ch.`	Automated Pipeline Transformations with Fluid Pipelines. Advanced Logic Synthesis Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau
2018	J	`jnl`	GPU NTC Process Variation Compensation With Voltage Stacking. IEEE Trans. Very Large Scale Integr. Syst. Rafael Trapani Possignolo, Elnaz Ebrahimi, Ehsan K. Ardestani, Alamelu Sankaranarayanan, José Luis Briz, Jose Renau
2017	A*	`conf`	Architectural opportunities for novel dynamic EMI shifting (DEMIS). MICRO Daphne I. Gorman, Matthew R. Guthaus, Jose Renau
2017	C	`conf`	Level shifter design for voltage stacking. ISCAS Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau
2017	C	`conf`	Liam: an actor based programming model for HDLs. MEMOCODE Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau
2017	A*	`conf`	LiveSynth: Towards an Interactive Synthesis Flow. DAC Rafael Trapani Possignolo, Jose Renau
2017	C	`conf`	Timing speculative SRAM. ISCAS Elnaz Ebrahimi, Matthew R. Guthaus, Jose Renau
2016	B	`conf`	Analysis of PARSEC workload scalability. ISPASS Gabriel Southern, Jose Renau
2016	C	`conf`	Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. ICCD Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau
2016	A*	`conf`	LiveSim: Going live with microarchitecture simulation. HPCA Sina Hassani, Gabriel Southern, Jose Renau
2016	—	`conf`	LiveSynth: Towards an interactive synthesis flow. Hot Chips Symposium Rafael Trapani Possignolo, Jose Renau
2016	J	`jnl`	Managing Mismatches in Voltage Stacking with CoreUnfolding. ACM Trans. Archit. Code Optim. Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz, Jose Renau
2016	—	`conf`	Overhead of deoptimization checks in the V8 javascript engine. IISWC Gabriel Southern, Jose Renau
2016	C	`conf`	SRAM voltage stacking. ISCAS Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau
2015	B	`conf`	Message from the program chair. ISPASS Jose Renau
2015	B	`conf`	Section based program analysis to reduce overhead of detecting unsynchronized thread communication. PPoPP Madan Mohan Das, Gabriel Southern, Jose Renau
2015	J	`jnl`	Section-Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication. ACM Trans. Archit. Code Optim. Madan Mohan Das, Gabriel Southern, Jose Renau
2014	J	`jnl`	Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices. IEEE Trans. Very Large Scale Integr. Syst. Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, Ali Shakouri
2013	A	`conf`	An energy efficient GPGPU memory hierarchy with tiny incoherent caches. ISLPED Alamelu Sankaranarayanan, Ehsan K. Ardestani, José Luis Briz, Jose Renau
2013	A*	`conf`	ESESC: A fast multicore simulator using Time-Based Sampling. HPCA Ehsan K. Ardestani, Jose Renau
2013	—	`conf`	ESESC: A fast performance, power, and temperature multicore simulator. Hot Chips Symposium Ehsan K. Ardestani, Gabriel Southern, Jason Doung, Elnaz Ebrahimi, Jose Renau
2013	J	`jnl`	Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ehsan K. Ardestani, Francisco J. Mesa-Martinez, Gabriel Southern, Elnaz Ebrahimi, Jose Renau
2012	A	`conf`	Thermal-aware sampling in architectural simulation. ISLPED Ehsan K. Ardestani, Elnaz Ebrahimi, Gabriel Southern, Jose Renau
2011	—	`conf`	A design time simulator for computer architects. ISQED Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, Jose Renau
2011	J	`jnl`	Hot Chips 22. IEEE Micro Jose Renau, Will Eatherton
2011	J	`jnl`	ReRack: power simulation for data centers with renewable energy generation. SIGMETRICS Perform. Evaluation Rev. Michael Brown, Jose Renau
2011	A*	`conf`	Releasing efficient beta cores to market early. ISCA Sangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau
2010	A*	`conf`	Characterizing processor thermal behavior. ASPLOS Francisco J. Mesa-Martinez, Ehsan K. Ardestani, Jose Renau
2009	A	`conf`	Measuring and modeling variabilityusing low-cost FPGAs. FPGA Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau
2009	A	`conf`	SOI, interconnect, package, and mainboard thermal characterization. ISLPED Joseph Nayfach-Battilana, Jose Renau
2008	A	`conf`	Measuring power and temperature from real processors. IPDPS Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau
2008	—	`conf`	Processor Verification with hwBugHunt. ISQED Sangeetha Sudhakrishnan, Liying Su, Jose Renau
2008	A	`conf`	Understanding bug fix patterns in verilog. MSR Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau
2007	A*	`conf`	Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. MICRO Francisco J. Mesa-Martinez, Jose Renau
2007	C	`conf`	Estimating design time for system circuits. VLSI-SoC Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau
2007	—	`conf`	Measuring performance, power, and temperature from real processors. Experimental Computer Science Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau
2007	A*	`conf`	Power model validation through thermal measurements. ISCA Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau
2007	—	`conf`	System and Procesor Design Effort Estimation. VLSI-SoC (Selected Papers) Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau
2006	J	`jnl`	CAVA: Using checkpoint-assisted value prediction to hide L2 misses. ACM Trans. Archit. Code Optim. Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau
2006	J	`jnl`	Energy-Efficient Thread-Level Speculation. IEEE Micro Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
2006	B	`conf`	POSH: a TLS compiler that exploits program structure. PPoPP Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas
2006	B	`conf`	SEED: scalable, efficient enforcement of dependences. PACT Francisco J. Mesa-Martinez, Michael C. Huang, Jose Renau
2005	A	`conf`	Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. ICS Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas
2005	A	`conf`	Thread-Level Speculation on a CMP can be energy efficient. ICS Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
2005	A*	`conf`	uComplexity: Estimating Processor Design Effort. MICRO Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau
2004	J	`jnl`	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction. IEEE Comput. Archit. Lett. Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas
2004	—	`—`	Chip Multiprocessors With Speculative Multithreading: Design for Performance and Energy Efficiency Jose Renau
2003	A*	`conf`	Positional Adaptation of Processors: Application to Energy Reduction. ISCA Michael C. Huang, Jose Renau, Josep Torrellas
2003	B	`conf`	Programming the FlexRAM parallel intelligent memory system. PPoPP Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas
2002	A*	`conf`	Cherry: checkpointed early resource recycling in out-of-order microprocessors. MICRO José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas
2002	A	`conf`	Energy-efficient hybrid wakeup logic. ISLPED Michael C. Huang, Jose Renau, Josep Torrellas
2001	A	`conf`	L1 data cache decomposition for energy efficiency. ISLPED Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
2001	J	`jnl`	The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. J. Instr. Level Parallelism Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
2000	A*	`conf`	A framework for dynamic energy efficiency and temperature management. MICRO Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
2000	—	`conf`	Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Intelligent Memory Systems Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas