Jos van Sas

12 papers A 6Journal 5Unranked 1
YearRankTypeTitle / Venue / Authors
1996 A conf
Towards an Effective I
ITC
Jos van Sas, Urbain Swerts, Marc Darquennes
1995 A conf
Coping with Re-usability Using Sequential ATPG: A Practical Case Study.
ITC
Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, Ad J. van de Goor
1994 A conf
An Off-chip I
ITC
Hans A. R. Manhaeve, Paul L. Wrighton, Jos van Sas, Urbain Swerts
1994 J jnl
Cellular automata based deterministic self-test strategies for programmable data paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jos van Sas, Francky Catthoor, Hugo De Man
1994 J jnl
Design of a C-testable booth multiplier using a realistic fault model.
J. Electron. Test.
Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man
1993 A conf
BIST for Embedded Static RAMs with Coverage Calculation.
ITC
Jos van Sas, Geert van Wauwe, Erik Huyskens, Dirk Rabaey
1993 J jnl
Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories.
IEEE Des. Test Comput.
Jos van Sas, Francky Catthoor, Hugo De Man
1992 A conf
Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata.
ITC
Jos van Sas, Francky Catthoor, Hugo De Man
1991 — conf
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment.
EURO-DAC
Jos van Sas, Francky Catthoor, Peter Vandeput, Frank Rossaert, Hugo De Man
1990 A conf
Cellular automata based self-test for programmable data paths.
ITC
Jos van Sas, Francky Catthoor, Hugo De Man
1990 J jnl
Testability strategy and test pattern generation for register files and customized memories.
Microprocess. Microsystems
Jos van Sas, Francky Catthoor, Luc Inzé, Hugo De Man
1989 J jnl
A testability strategy for multiprocessor architecture.
IEEE Des. Test
Francky Catthoor, Jos van Sas, Luc Inzé, Hugo De Man