Jorgen Peddersen

30 papers A* 2A 5B 2C 2Misc 5Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2020 J jnl
FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vikkitharan Gnanasambandapillai, Jorgen Peddersen, Roshan G. Ragel, Sri Parameswaran
2015 J jnl
CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique.
CoRR
Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
2015 J jnl
DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy.
CoRR
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2015 A conf
E-pipeline: elastic hardware/software pipelines on a many-core fabric.
DATE
Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel, Sri Parameswaran
2015 C conf
RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory.
ICCD
Su Myat Min Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen, Sri Parameswaran
2015 C conf
Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications.
ICCD
Jude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran
2015 — conf
Speeding up single pass simulation of PLRUt caches.
ASP-DAC
Josef Schneider, Jorgen Peddersen, Sri Parameswaran
2014 — conf
A scorchingly fast FPGA-based Precise L1 LRU cache simulator.
ASP-DAC
Josef Schneider, Jorgen Peddersen, Sri Parameswaran
2014 A* conf
MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis.
DAC
Josef Schneider, Jorgen Peddersen, Sri Parameswaran
2014 — conf
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs.
ASP-DAC
Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide
2013 — conf
A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES.
ISVLSI
Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
2013 — conf
DRMA: dynamically reconfigurable MPSoC architecture.
ACM Great Lakes Symposium on VLSI
Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja
2012 Misc conf
A Rapid Methodology for Multi-mode Communication Circuit Generation.
VLSI Design
Liang Tang, Jorgen Peddersen, Sri Parameswaran
2011 A conf
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique.
ICCAD
Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
2011 Misc conf
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction.
VLSI Design
Su Myat Min, Jorgen Peddersen, Sri Parameswaran
2010 A conf
ACS: Automatic Converter Synthesis for SoC Bus Protocols.
TACAS
Karin Avnit, Arcot Sowmya, Jorgen Peddersen
2010 A conf
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.
DATE
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2010 A conf
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm.
DATE
Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran
2010 B conf
Improved Architectures for Range Encoding in Packet Classification System.
NCA
Xin He, Jorgen Peddersen, Sri Parameswaran
2010 J jnl
LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM.
Des. Autom. Embed. Syst.
Xin He, Jorgen Peddersen, Sri Parameswaran
2010 — conf
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors.
DIPES/BICC
Roshan G. Ragel, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
2010 A* conf
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.
DAC
Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2009 Misc conf
LOP: a novel SRAM-based architecture for low power and high throughput packet classification.
CODES+ISSS
Xin He, Jorgen Peddersen, Sri Parameswaran
2009 B conf
LOP_RE: Range encoding for low power packet classification.
LCN
Xin He, Jorgen Peddersen, Sri Parameswaran
2008 J jnl
Energy Driven Application Self-Adaptation at Run-time.
J. Comput.
Jorgen Peddersen, Sri Parameswaran
2008 J jnl
Low-Impact Processor for Dynamic Runtime Power Management.
IEEE Des. Test Comput.
Jorgen Peddersen, Sri Parameswaran
2008 — —
Run-time energy-driven optimisation of embedded systems: a complete solution.
Jorgen Peddersen
2007 — conf
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time.
ASP-DAC
Jorgen Peddersen, Sri Parameswaran
2007 Misc conf
Energy Driven Application SelfAdaptation.
VLSI Design
Jorgen Peddersen, Sri Parameswaran
2005 Misc conf
Rapid Embedded Hardware/Software System Generation.
VLSI Design
Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran