Jorge Juan - RankMe

11 papers B 1C 1Journal 5Unranked 4

Year	Rank	Type	Title / Venue / Authors
2017	J	`jnl`	Minimalistic SDHC-SPI hardware reader module for boot loader applications. Microelectron. J. Paulino Ruiz-de-Clavijo, Enrique Ostúa, Manuel Jesús Bellido Díaz, Jorge Juan, Julian Viejo, David Guerrero Martos
2012	J	`jnl`	Long-term on-chip verification of systems with logical events scattered in time. Microprocess. Microsystems Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Enrique Ostúa, Juan Quiros
2012	—	`conf`	Network Time Synchronization: A Full Hardware Approach. PATMOS Jorge Juan, Julian Viejo, Manuel J. Bellido
2011	J	`jnl`	Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE Trans. Instrum. Meas. Julian Viejo, Jorge Juan, Manuel Jesús Bellido Díaz, Alejandro Millán, Paulino Ruiz-de-Clavijo
2011	J	`jnl`	Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
2010	J	`jnl`	Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electron. Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
2010	—	`conf`	Design and implementation of a suitable core for on-chip long-term verification. SIES Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa
2009	B	`conf`	Efficient techniques and methodologies for embedded system design usign free hardware and open standards. FPL Jose Ignacio Villar, Jorge Juan, Manuel J. Bellido
2008	—	`conf`	Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
2007	—	`conf`	Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz
2006	C	`conf`	Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos