Joonas Multanen

29 papers A 1C 1Journal 11Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions. IEEE Trans. Very Large Scale Integr. Syst. Kari Hepola, Tharaka Ranasinghe Arachchige, Joonas Multanen, Pekka Jääskeläinen
2024	J	`jnl`	Bitstream Database-Driven FPGA Programming Flow Based on Standard OpenCL. IEEE Trans. Very Large Scale Integr. Syst. Topi Leppänen, Leevi Leppänen, Joonas Multanen, Pekka Jääskeläinen
2024	—	`conf`	Cycle Count Estimation of VLIW Processors Using Machine Learning. NorCAS Kari Hepola, Jatan Shrestha, Joonas Multanen, Vivienne Wang, Joni Pajarinen, Pekka Jääskeläinen
2024	J	`jnl`	Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode. IEEE Trans. Computers Kari Hepola, Joonas Multanen, Pekka Jääskeläinen
2024	J	`jnl`	Energy-efficient instruction compression with programmable dictionaries. Des. Autom. Embed. Syst. Joonas Multanen, Barry de Bruin, Henk Corporaal, Pekka Jääskeläinen
2024	—	`conf`	Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom Instructions. NorCAS Kari Hepola, Tharaka Ranasinghe Arachchige, Joonas Multanen, Pekka Jääskeläinen
2024	—	`conf`	Towards Efficient OpenCL Pipe Specification for Hardware Accelerators. IWOCL Topi Leppänen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen
2023	J	`jnl`	AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors. J. Signal Process. Syst. Alex Hirvonen, Topi Leppänen, Kari Hepola, Joonas Multanen, Joost Hoozemans, Pekka Jääskeläinen
2023	—	`conf`	AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management. NorCAS Topi Leppänen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen
2023	J	`jnl`	Efficient OpenCL system integration of non-blocking FPGA accelerators. Microprocess. Microsystems Topi Leppänen, Atro Lotvonen, Panagiotis Mousouliotis, Joonas Multanen, Georgios Keramidas, Pekka Jääskeläinen
2022	—	`conf`	Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism. ARCS Kari Hepola, Joonas Multanen, Pekka Jääskeläinen
2022	J	`jnl`	Energy-Efficient Instruction Delivery in Embedded Systems With Domain Wall Memory. IEEE Trans. Computers Joonas Multanen, Kari Hepola, Asif Ali Khan, Jerónimo Castrillón, Pekka Jääskeläinen
2022	—	`conf`	OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors. ASAP Kari Hepola, Joonas Multanen, Pekka Jääskeläinen
2021	—	`—`	Energy-Efficient Instruction Streams for Embedded Processors. Joonas Multanen
2021	—	`conf`	Unified OpenCL Integration Methodology for FPGA Designs. NorCAS Topi Leppänen, Panagiotis Mousouliotis, Georgios Keramidas, Joonas Multanen, Pekka Jääskeläinen
2020	J	`jnl`	Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications. J. Signal Process. Syst. Joonas Multanen, Heikki Kultala, Kati Tervo, Pekka Jääskeläinen
2020	C	`conf`	Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency. ICCD Joonas Multanen, Kari Hepola, Pekka Jääskeläinen
2020	—	`conf`	System Simulation of Memristor Based Computation in Memory Platforms. SAMOS Ali BanaGozar, Kanishkan Vadivel, Joonas Multanen, Pekka Jääskeläinen, Sander Stuijk, Henk Corporaal
2019	J	`jnl`	LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor. IEEE Trans. Very Large Scale Integr. Syst. Heikki Kultala, Timo Viitanen, Heikki Berg, Pekka Jääskeläinen, Joonas Multanen, Mikko Kokkonen, Kalle Raiskila, Tommi Zetterman, Jarmo Takala
2019	A	`conf`	SHRIMP: Efficient Instruction Delivery with Domain Wall Memory. ISLPED Joonas Multanen, Pekka Jääskeläinen, Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón
2018	—	`conf`	Energy-Delay Trade-Offs in Instruction Register File Design. NORCAS Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen
2018	J	`jnl`	Instantaneous foveated preview for progressive Monte Carlo rendering. Comput. Vis. Media Matias Koskela, Kalle Immonen, Timo Viitanen, Pekka Jääskeläinen, Joonas Multanen, Jarmo H. Takala
2018	J	`jnl`	Instruction Fetch Energy Reduction with Biased SRAMs. J. Signal Process. Syst. Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala
2018	—	`conf`	LoTTA: Energy-Efficient Processor for Always-On Applications. SiPS Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen, Timo Viitanen, Aleksi Tervo, Jarmo Takala
2017	—	`conf`	Foveated instant preview for progressive rendering. SIGGRAPH Asia Technical Briefs Matias Koskela, Kalle Immonen, Timo Viitanen, Pekka Jääskeläinen, Joonas Multanen, Jarmo Takala
2016	—	`conf`	Customized high performance low power processor for binaural speaker localization. ICECS Nicolai Behmann, Christopher Seifert, Guillermo Payá-Vayá, Holger Blume, Pekka Jääskeläinen, Joonas Multanen, Heikki Kultala, Jarmo Takala, Joachim Thiemann, Steven van de Par
2016	—	`conf`	OpenCL programmable exposed datapath high performance low-power image signal processor. NORCAS Joonas Multanen, Heikki Kultala, Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala, Aram Danielyan, Cristóvão Cruz
2016	—	`conf`	Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies. SiPS Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala
2015	—	`conf`	Power optimizations for transport triggered SIMD processors. SAMOS Joonas Multanen, Timo Viitanen, Henry Linjamaki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskinen, Jesse Simonsson, Heikki Berg, Kalle Raiskila, Tommi Zetterman