Jooeun Bang

11 papers Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces.
IEEE J. Solid State Circuits
Jaeho Kim, Myeongho Han, Hyunjun Song, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
2025 — conf
8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time.
ISSCC
Jaeho Kim, Myeongho Han, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
2025 J jnl
A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer With a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier.
IEEE J. Solid State Circuits
Seohee Jung, Jaeho Kim, Jooeun Bang, Sarang Lee, Heein Yoon, Jaehyouk Choi
2025 J jnl
A Low-Reference-Spur and Low-Jitter D-Band PLL With Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector.
IEEE Solid State Circuits Lett.
Jaeho Kim, Jooeun Bang, Seohee Jung, Myeongho Han, Jaehyouk Choi
2024 — conf
A -51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector.
A-SSCC
Jaeho Kim, Jooeun Bang, Seohee Jung, Myeongho Han, Jaehyouk Choi
2023 — conf
A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth.
ISSCC
Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi
2022 J jnl
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop.
IEEE J. Solid State Circuits
Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Jaehyouk Choi
2021 — conf
A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency.
ESSCIRC
Jooeun Bang, Seojin Choi, Seyeon Yoo, Jeonghyun Lee, Juyeop Kim, Jaehyouk Choi
2020 — conf
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator.
ISSCC
Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Seyeon Yoo, Hangi Park, Heein Yoon, Jaehyouk Choi
2019 — conf
A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer.
VLSI Circuits
Jeonghyun Lee, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
2018 — conf
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers.
ISSCC
Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi