Joo-Sun Choi

35 papers A* 2C 1Journal 13Unranked 19
YearRankTypeTitle / Venue / Authors
2017 A* conf
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.
HPCA
Sang-uhn Cha, Seongil O, Hyunsung Shin, Sangjoon Hwang, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Gyo-Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, Nam Sung Kim
2015 — conf
17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs.
ISSCC
Won-Joo Yun, Indal Song, Hanki Jeoung, Hundai Choi, Seok-Ho Lee, Jun-Bae Kim, Chi-Wook Kim, Jung-Hwan Choi, Seong-Jin Jang, Joo-Sun Choi
2015 — conf
5.7 A 29nW bandgap reference circuit.
ISSCC
Jongmi Lee, Youngwoo Ji, Seungnam Choi, Young-Chul Cho, Seong-Jin Jang, Joo-Sun Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
2015 J jnl
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.
IEEE J. Solid State Circuits
Tae-Young Oh, Hoeju Chung, Jun-Young Park, Ki-Won Lee, Seung-Hoon Oh, Su-Yeon Doo, Hyoung-Joo Kim, Changyong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-Soo Ha, Young-Ryeol Choi, Young-Chul Cho, Yong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwang-Il Park, SeongJin Jang, Joo-Sun Choi
2015 A* conf
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.
DAC
Yarui Peng, Bon Woong Ku, Youn-Sik Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Sung Kyu Lim
2014 — conf
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
ISSCC
Tae-Young Oh, Hoeju Chung, Young-Chul Cho, Jang-Woo Ryu, Kiwon Lee, Changyoung Lee, Jin-Il Lee, Hyoung-Joo Kim, Min-Soo Jang, Gong-Heum Han, Kihan Kim, Daesik Moon, Seung-Jun Bae, Joon-Young Park, Kyung-Soo Ha, Jaewoong Lee, Su-Yeon Doo, Jung-Bum Shin, Chang-Ho Shin, Kiseok Oh, Doo-Hee Hwang, Taeseong Jang, Chulsung Park, Kwang-Il Park, Jung-Bae Lee, Joo-Sun Choi
2014 J jnl
CMOS Charge Pump With No Reversion Loss and Enhanced Drivability.
IEEE Trans. Very Large Scale Integr. Syst.
Joung-Yeal Kim, Su-Jin Park, Kee-Won Kwon, Bai-Sun Kong, Joo-Sun Choi, Young-Hyun Jun
2014 — conf
Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs.
VLSIC
Reum Oh, ByungHyun Lee, Sang-Woong Shin, Wonil Bae, Hundai Choi, Indal Song, Yun-Sang Lee, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Joo-Sun Choi
2013 J jnl
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.
IEEE J. Solid State Circuits
Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Seok-Hun Hyun, Hanki Jeoung, Ki Won Lee, Jun-Seok Park, Jongeun Lee, ByungHyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Byungchul Kim, Jung-Hwan Choi, Seong-Jin Jang, Chi-Wook Kim, Jung-Bae Lee, Joo-Sun Choi
2013 — conf
An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme.
ISSCC
Ji-Hwan Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, Lee-Sup Kim
2013 — conf
Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module.
SoCC
Seung Mo Jung, Jong Hyun Seok, Ho Jin Yoo, Do Hyung Kim, You Keun Han, Woo-Seop Kim, Joo-Sun Choi, Jun Dong Cho
2012 J jnl
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking.
IEEE J. Solid State Circuits
Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo-Sun Choi, Young-Hyun Jun
2012 — conf
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.
ISSCC
Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung-Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Young Hoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo-Sun Choi, Kyungseok Oh
2012 — conf
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme.
ISSCC
Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki Won Lee, Junsuk Park, Jongeun Lee, ByungHyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byung-Sick Moon, Jung-Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo-Sun Choi, Kyungseok Oh
2012 — conf
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.
ISSCC
Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong-June Park, Jae-Yoon Sim
2012 — conf
Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee.
ISSCC
Joo-Sun Choi, Daisaburo Takashima
2011 — conf
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking.
ISSCC
Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kyehyun Kyung, Joo-Sun Choi, Young-Hyun Jun
2011 — conf
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.
ISSCC
Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim, Sang-Hyup Kwak, Ho-Seok Seol, Chang-Ho Shin, Min-Sang Park, Gong-Heom Han, Byeong-Cheol Kim, Yong-Ki Cho, Hye-Ran Kim, Su-Yeon Doo, Young-Sik Kim, Dong-Seok Kang, Young-Ryeol Choi, Sam-Young Bang, Sun-Young Park, Yong-Jae Shin, Gil-Shin Moon, Cheol-Goo Park, Woo-Seop Kim, Hyang-Ja Yang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun
2011 J jnl
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
IEEE J. Solid State Circuits
Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun
2011 J jnl
An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs.
IEICE Trans. Electron.
Jong-Pil Son, Jin Ho Kim, Woo Song Ahn, Seung Uk Han, Satoru Yamada, Byung-Sick Moon, Churoo Park, Hong-Sun Hwang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Soo-Won Kim
2010 J jnl
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.
IEEE J. Solid State Circuits
Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jae-Wook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun
2010 — conf
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.
ISSCC
Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun
2010 — conf
A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.
CICC
Jun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park
2010 — conf
A highly reliable multi-cell antifuse scheme using DRAM cell capacitors.
ESSCIRC
Jong-Pil Son, Jin Ho Kim, Woo Song Ahn, Seung Uk Han, Byung-Sick Moon, Churoo Park, Hong-Sun Hwang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Soo-Won Kim
2010 J jnl
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232].
IEEE J. Solid State Circuits
Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim
2010 — conf
Silicon 3D-integration technology and systems.
ISSCC
Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo-Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai
2009 J jnl
A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN.
IEEE J. Solid State Circuits
Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim
2009 J jnl
A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme.
IEEE J. Solid State Circuits
Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim
2009 — conf
A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces.
ISSCC
Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim
2008 — conf
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.
ISSCC
Seung-Jun Bae, Young-Soo Sohn, Kwang-Il Park, Kyoung-Ho Kim, Dae-Hyun Chung, Jingook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim, Hye-Ran Kim, Yong-Jae Shin, Cheol-Goo Park, Gil-Shin Moon, Ki-Woong Yeom, Kang-Young Kim, Jae-Young Lee, Hyang-Ja Yang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim
2008 J jnl
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits
Seung-Jun Bae, Kwang-Il Park, Jeong-Don Ihm, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Yoon-Sik Park, Min-Sang Park, Hong-Kyong Lee, Sam-Young Bang, Gil-Shin Moon, Seokwon Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim, Ji-Hoon Lim, Jae-Sung Kim, Sunghoon Kim, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim, Soo-In Cho
2008 C conf
PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion.
ISCAS
Youn-Sik Park, Sung-Wook Lee, Bai-Sun Kong, Kwang-Il Park, Jeong-Don Ihm, Joo-Sun Choi, Young-Hyun Jun
2007 J jnl
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits
Kyu-Hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim
2006 — conf
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
ISSCC
Kyu-Hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim
1996 J jnl
Charge recycling differential logic (CRDL) for low power application.
IEEE J. Solid State Circuits
Bai-Sun Kong, Joo-Sun Choi, Seog-Jun Lee, Kwyro Lee