Joo-Hyung Chae

51 papers A 3C 2Journal 31Unranked 15
YearRankTypeTitle / Venue / Authors
2026 — conf
37.6 A 0.092pJ/b and 7.7fJ/b/dB Cross-Self-Referenced Slope-Sampling Receiver with Long-Tail ISI Robustness for Next-Generation Low-Power Memory Interfaces.
ISSCC
Ki-Soo Lee, Chanheum Han, Joo-Hyung Chae
2026 J jnl
DPIM: A 2T1C eDRAM Transformer-in-Memory Chip With Sparsity-Aware Quantization and Heterogeneous Dense-Sparse Core.
IEEE J. Solid State Circuits
Donghyuk Kim, Jae-Young Kim, Hyunjun Cho, Seungjae Yoo, Sukjin Lee, Sungwoong Yune, Sejeong Yang, Hoichang Jeong, Keonhee Park, Ki-Soo Lee, Jongchan Lee, Chanheum Han, Gunmo Koo, Yuli Han, Jaejin Kim, Jaemin Kim, Kyuho Jason Lee, Joo-Hyung Chae, Kunhee Cho, Joo-Young Kim
2025 J jnl
25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies.
IEEE J. Solid State Circuits
Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae
2025 — conf
A 0.9-V 15.6-Gb/s Single Ended NRZ Receiver with 1-Tap DFE for Low-Power Memory Interfaces.
ICEIC
Jongmin Lee, Ki-Soo Lee, Joo-Hyung Chae
2025 — conf
A 1.05-V/0.5-V 15.6-Gb/s NRZ Transmitter Achieving 0.76-pJ/bit Energy Efficiency for Low-Power Memory Interfaces.
ICEIC
Ju-Hyeong Yun, Yong-Gyu Yu, Jongchan Lee, Joo-Hyung Chae
2025 J jnl
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Cross-Coupled Pre-Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ik-Hyeon Jeon, Joo-Hyung Chae
2025 J jnl
A Dual-Multiplication-Mode and Reconfigurable Digital Compute-in-Memory Macro Using Precharge-Controlled 4T1C eDRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Ho-Sung Lee, Ik-Hyeon Jeon, Jiwon Lee, Eun-Bi Koh, Joo-Hyung Chae
2025 J jnl
A V
IEEE Trans. Circuits Syst. I Regul. Pap.
Chanheum Han, Ki-Soo Lee, Jun-Cheol Lee, Joo-Hyung Chae
2025 J jnl
Sub 0.1-pJ/bit 14-Gb/s Receiver With Stack-Reduced Slicer Embedding One-Tap DFE for Low-Power Memory Interfaces.
IEEE Trans. Very Large Scale Integr. Syst.
Ki-Soo Lee, Joo-Hyung Chae
2025 — conf
SystemVerilog-Based Modeling and Verification of 25.6-GBaud/Lane PAM-3 Receiver.
SMACD
Chae-Hyeon Lim, Ju-Hyeong Yun, Yong-Gyu Yu, Joo-Hyung Chae
2025 — conf
SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 Transmitter for USB4.0 Gen4.
SMACD
Yong-Gyu Yu, Ju-Hyeong Yun, Chae-Hyeon Lim, Joo-Hyung Chae
2025 J jnl
URcon: Unified and Reconfigurable Control and Verification Platform for Multi-Mode Customized eDRAM and SRAM Macros.
IEEE Access
Ho-Sung Lee, Ik-Hyeon Jeon, Jiwon Lee, Hyeonjun Cheon, Joo-Hyung Chae
2024 — conf
13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency.
ISSCC
Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae
2024 — conf
A 1-Kb 6T 1C XNOR-DRAM Compute-In-Memory Macro With Signed Bit Adder Block for CNN Operations.
ICEIC
Ho-Sung Lee, Joo-Hyung Chae
2024 — conf
A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access Modes.
ISOCC
Hyeonjun Cheon, Ho-Sung Lee, Jiwon Lee, Ik-Hyeon Jeon, Joo-Hyung Chae
2024 J jnl
A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces.
IEEE J. Solid State Circuits
Jaekwang Yun, Sangyoon Lee, Jaewook Kim, Joo-Hyung Chae, Suhwan Kim, Yong-Un Jeong
2024 J jnl
A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yong-Un Jeong, Joo-Hyung Chae
2024 J jnl
Debugging Circuit for Detecting Timing Errors in Serializer for High-Speed Wireline Interfaces.
IEEE Access
Jongchan Lee, Joo-Hyung Chae
2024 — conf
Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation Speed.
ISOCC
Jiwon Lee, Hyeonjun Cheon, Ho-Sung Lee, Ik-Hyeon Jeon, Joo-Hyung Chae
2024 J jnl
Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory Interfaces.
IEEE Trans. Instrum. Meas.
Yong-Un Jeong, Joo-Hyung Chae
2023 J jnl
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces.
IEEE J. Solid State Circuits
Yong-Un Jeong, Joo-Hyung Chae, Suhwan Kim
2023 J jnl
A 50-1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line.
IEEE Access
Jaewook Kim, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim
2023 J jnl
Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement.
IEEE Trans. Instrum. Meas.
Joo-Hyung Chae
2023 — conf
Module Implementation and Simulation of Timing Constraint Check Function of I2C Protocol Using Verilog.
ICEIC
Jun-Cheol Lee, Tae-Oh Kim, Joo-Hyung Chae
2023 J jnl
Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yong-Un Jeong, Sungphil Choi, Suhwan Kim, Joo-Hyung Chae
2022 J jnl
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yong-Un Jeong, Sungphil Choi, Joo-Hyung Chae, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim
2022 J jnl
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits
Jihyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha
2022 J jnl
A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching.
IEEE Trans. Circuits Syst. II Express Briefs
Sangyoon Lee, Yong-Un Jeong, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim
2022 J jnl
Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters.
IEEE Access
Joo-Hyung Chae, Yong-Un Jeong, Byung-Du Choi
2021 J jnl
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface.
IEEE J. Solid State Circuits
Yong-Un Jeong, Hyunkyu Park, Changho Hyun, Joo-Hyung Chae, Shin-Hyun Jeong, Suhwan Kim
2021 — conf
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
ISSCC
Kyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Jihyo Kang, Gang-Sik Lee, Sang-Yeon Byeon, Youngtaek Kim, Boram Kim, Dong-Hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park, Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sangkwon Lee, Junhyun Chun, Hyungsoo Kim, Seon-Yong Cha
2021 J jnl
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer.
IEEE J. Solid State Circuits
Hyeongjun Ko, Mino Kim, Hyunkyu Park, Sangyoon Lee, Jaewook Kim, Suhwan Kim, Joo-Hyung Chae
2021 J jnl
A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface.
IEEE Access
Sungphil Choi, Yong-Un Jeong, Joo-Hyung Chae, Shin-Hyun Jeong, Suhwan Kim
2021 C conf
A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces.
ISCAS
Hyunkyu Park, Jihwan Park, Jae-Whan Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim, Joo-Hyung Chae
2020 J jnl
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation.
IEEE Trans. Circuits Syst. II Express Briefs
Sangyoon Lee, Han-Gon Ko, Joo-Hyung Chae, Soyeong Shin, Jaekwang Yun, Deog-Kyoon Jeong, Suhwan Kim
2020 J jnl
A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Joo-Hyung Chae, Minchang Kim, Sungphil Choi, Suhwan Kim
2020 J jnl
A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Yong-Un Jeong, Jihwan Park, Mino Kim, Joo-Hyung Chae, Jaekwang Yun, Hyunjoong Lee, Suhwan Kim
2020 J jnl
Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Joo-Hyung Chae, Yong-Un Jeong, Suhwan Kim
2019 J jnl
A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner.
IEEE Trans. Circuits Syst. II Express Briefs
Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim
2019 C conf
A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation.
ISCAS
Changho Hyun, Hyeongjun Ko, Joo-Hyung Chae, Hyunkyu Park, Suhwan Kim
2019 A conf
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS.
ISLPED
Yong-Un Jeong, Joo-Hyung Chae, Sungphil Choi, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim
2019 J jnl
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator.
IEEE Trans. Very Large Scale Integr. Syst.
Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim
2018 J jnl
A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface.
IEEE J. Solid State Circuits
Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim
2018 J jnl
A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization.
IEEE Access
Joo-Hyung Chae, Mino Kim, Gi-Moon Hong, Jihwan Park, Suhwan Kim
2018 J jnl
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller.
IEEE Trans. Circuits Syst. II Express Briefs
Mino Kim, Joo-Hyung Chae, Sungphil Choi, Gi-Moon Hong, Hyeongjun Ko, Deog-Kyoon Jeong, Suhwan Kim
2018 A conf
Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces.
ISLPED
Jae-Whan Lee, Joo-Hyung Chae, Jihwan Park, Hyunkyu Park, Jaekwang Yun, Suhwan Kim
2017 A conf
A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication.
ISLPED
Jihwan Park, Gi-Moon Hong, Mino Kim, Joo-Hyung Chae, Suhwan Kim
2017 — conf
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface.
A-SSCC
Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim
2017 — conf
An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface.
ISOCC
Minchang Kim, Jihwan Park, Joo-Hyung Chae, Hyeongjun Ko, Mino Kim, Suhwan Kim
2015 — conf
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.
A-SSCC
Joo-Hyung Chae, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim
2013 — conf
High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line.
ESSCIRC
Mino Kim, Woo-Yeol Shin, Gi-Moon Hong, Jihwan Park, Joo-Hyung Chae, Nan Xing, Jong-Kwan Woo, Suhwan Kim