Jongsun Park - RankMe

175 papers A* 11A 14B 2C 13Misc 2Journal 89Unranked 44

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	ROZK: An Energy-Efficient DNN Accelerator Based on Reconfigurable NoC and Local Zero-Skipping. IEEE J. Solid State Circuits Heetak Kim, Yunpyo Hong, Byungsoo Kim, Jongsun Park
2026	J	`jnl`	Speeding-Up Successive Read Operations of STT-MRAM via Read Path Alternation for Delay Symmetry. IEEE Trans. Circuits Syst. I Regul. Pap. Taehwan Kim, Seunghwa Hyun, Jangseok Yu, Jongsun Park
2025	J	`jnl`	A Design Framework of Heterogeneous Approximate DCIM-Based Accelerator for Energy-Efficient NN Processing. IEEE Trans. Circuits Syst. I Regul. Pap. Kyeongho Lee, Hyeyeong Lee, Jongsun Park
2025	C	`conf`	A Pre-charge based Data Cell Dynamic Reference Sensing Scheme for Reliable Read Operations in STT-MRAM. ISCAS Kyongsoo Kim, Taehwan Kim, Jongsun Park
2025	J	`jnl`	Big-Computing and Little-Storing STT-MRAM PIM Architecture With Charge Domain Based MAC Operation. IEEE Trans. Computers Yunho Jang, Dongsu Kim, Yeseul Kim, Jongsun Park
2025	J	`jnl`	Bitline-Paired 2T SOT-MRAM Cell for Energy-Efficient Memory Operation. IEEE Trans. Very Large Scale Integr. Syst. Taehwan Kim, Jongsun Park
2025	J	`jnl`	CAT SNN: Conversion Aware Training for High Accuracy and Hardware Friendly Spiking Neural Networks. IEEE Trans. Emerg. Top. Comput. Dongwoo Lew, Jongsun Park
2025	J	`jnl`	DBB-ECC: Random Double Bit and Burst Error Correction Code for HBM3. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chaehyeon Shin, Jongsun Park
2025	—	`conf`	DPP-ViT: Dynamic Patch Pruning for Low Complexity Vision Transformer Accelerator. AICAS Han Cho, Joongho Jo, Seung-Eon Hwang, Jongsun Park
2025	J	`jnl`	Fault Bounding On-Die BCH Codes for Improving Reliability of System ECC. IEEE Trans. Very Large Scale Integr. Syst. Seongyoon Kang, Chaehyeon Shin, Jongsun Park
2025	A*	`conf`	GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learning. DAC Dongjun Kim, Junwoo Park, Chaehyeon Shin, Jaeheon Jung, Kyungho Shin, Seungheon Baek, Sanghyuk Heo, Woongrae Kim, In-Chul Jeong, Joohwan Cho, Jongsun Park
2025	J	`jnl`	GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learning. CoRR Dongjun Kim, Junwoo Park, Chaehyeon Shin, Jaeheon Jung, Kyungho Shin, Seungheon Baek, Sanghyuk Heo, Woongrae Kim, In-Chul Jeong, Joohwan Cho, Jongsun Park
2025	A*	`conf`	GS-TG: 3D Gaussian Splatting Accelerator with Tile Grouping for Reducing Redundant Sorting while Preserving Rasterization Efficiency. DAC Joongho Jo, Jongsun Park
2025	J	`jnl`	GS-TG: 3D Gaussian Splatting Accelerator with Tile Grouping for Reducing Redundant Sorting while Preserving Rasterization Efficiency. CoRR Joongho Jo, Jongsun Park
2025	J	`jnl`	Generative AI Through CAS Lens: An Integrated Overview of Algorithmic Optimizations, Architectural Advances, and Automated Designs. IEEE J. Emerg. Sel. Topics Circuits Syst. Chuan Zhang, You You, Naigang Wang, Jongsun Park, Li Zhang
2025	J	`jnl`	Guest Editorial Generative Artificial Intelligence Compute: Algorithms, Implementations, and Applications to CAS. IEEE J. Emerg. Sel. Topics Circuits Syst. Chuan Zhang, Naigang Wang, Jongsun Park, Li Zhang
2025	A	`conf`	PS-GS: Group-Wise Parallel Rendering with Stage-Wise Complexity Reductions for Real-Time 3D Gaussian Splatting. DATE Joongho Jo, Jongsun Park
2025	A	`conf`	SiGNoR: Similarity-based Graph Partitioning and Node Reuse for Memory Efficient GNN Acceleration. ICCAD Seung-Eon Hwang, Hyeon Gwon Kim, Dongwoo Lew, Jongsun Park
2025	A	`conf`	Speeding-Up Successive Read Operations of STT-MRAM via Read Path Alternation for Delay Symmetry. DATE Taehwan Kim, Jongsun Park
2025	—	`conf`	Tru-Sign: Lossless Truncated Sign Based Energy Efficient DNN Accelerator. AICAS Kyungchul Lee, Dongwoo Lew, Jongsun Park
2024	J	`jnl`	A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations. IEEE J. Solid State Circuits Kyeongho Lee, Joonhyung Kim, Jongsun Park
2024	C	`conf`	HeNCoG: A Heterogeneous Near-memory Computing Architecture for Energy Efficient GCN Acceleration. ISCAS Seung-Eon Hwang, Duyeong Song, Jongsun Park
2024	J	`jnl`	SOT-MRAM-Based LUT Cell Design for Area- and Energy-Efficient FPGA. IEEE Trans. Circuits Syst. II Express Briefs Dongsu Kim, Taehwan Kim, Yunho Jang, Jongsun Park
2024	A	`conf`	STT-MRAM-based Near-Memory Computing Architecture with Read Scheme and Dataflow Co-Design for High-Throughput and Energy-Efficiency. ISLPED Yunho Jang, Yeseul Kim, Jongsun Park
2024	A*	`conf`	SpARC: Token Similarity-Aware Sparse Attention Transformer Accelerator via Row-wise Clustering. DAC Han Cho, Dongjun Kim, Seung-Eon Hwang, Jongsun Park
2024	A	`conf`	TP-DCIM: Transposable Digital SRAM CIM Architecture for Energy-Efficient and High Throughput Transformer Acceleration. ICCAD Junwoo Park, Kyeongho Lee, Jongsun Park
2024	A	`conf`	iSPADE: End-to-end Sparse Architecture for Dense DNN Acceleration via Inverted-bit Representation. ISLPED Dongjun Kim, Han Cho, Jongsun Park
2023	J	`jnl`	A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Sungsoo Cheon, Kyeongho Lee, Jongsun Park
2023	J	`jnl`	LoCoExNet: Low-Cost Early Exit Network for Energy Efficient CNN Accelerator Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Joongho Jo, Geonho Kim, Seungtae Kim, Jongsun Park
2023	J	`jnl`	Low Area and Low Power Threshold Implementation Design Technique for AES S-Box. IEEE Trans. Circuits Syst. II Express Briefs Junhyun Song, Kyeongho Lee, Jongsun Park
2023	J	`jnl`	Low Complexity Gradient Computation Techniques to Accelerate Deep Neural Network Training. IEEE Trans. Neural Networks Learn. Syst. Dongyeob Shin, Geonho Kim, Joongho Jo, Jongsun Park
2022	—	`conf`	A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. AICAS Hyunchul Park, Kyeongho Lee, Jongsun Park
2022	A	`conf`	A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. ISLPED Joonhyung Kim, Kyeongho Lee, Jongsun Park
2022	J	`jnl`	A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. CoRR Joonhyung Kim, Kyeongho Lee, Jongsun Park
2022	J	`jnl`	A Dual-Domain Dynamic Reference Sensing for Reliable Read Operation in SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Jooyoon Kim, Yunho Jang, Taehwan Kim, Jongsun Park
2022	—	`conf`	A Layer-wise Training and Pruning Method for Memory Efficient On-chip Learning Hardware. ISOCC Dongwoo Lew, Jongsun Park
2022	J	`jnl`	A Time-to-first-spike Coding and Conversion Aware Training for Energy-Efficient Deep Spiking Neural Network Processor Design. CoRR Dongwoo Lew, Kyungchul Lee, Jongsun Park
2022	A*	`conf`	A time-to-first-spike coding and conversion aware training for energy-efficient deep spiking neural network processor design. DAC Dongwoo Lew, Kyungchul Lee, Jongsun Park
2022	J	`jnl`	Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing With Adjacent Cells. IEEE Trans. Circuits Syst. II Express Briefs Yunho Jang, Jongsun Park
2022	—	`conf`	BiMDiM: Area efficient Bi-directional MRAM Digital in-Memory Computing. AICAS Dongsu Kim, Yunho Jang, Taehwan Kim, Jongsun Park
2022	—	`conf`	Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations. ISOCC Hyunchul Park, Jongsun Park
2022	—	`conf`	Channel-Wise Activation Map Pruning using Max-Pool for Reducing Memory Accesses. ISOCC Han Cho, Jongsun Park
2022	—	`conf`	Class Difficulty based Mixed Precision Quantization for Low Complexity CNN Training. ISOCC Joongho Jo, Jongsun Park
2022	—	`conf`	Clipped Quantization Aware Training for Hardware Friendly Implementation of Image Classification Networks. ISOCC Kyungchul Lee, Jongsun Park
2022	—	`conf`	Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus. ISOCC Seongyoon Kang, Jongsun Park
2022	—	`conf`	Distributed Accumulation based Energy Efficient STT-MRAM based Digital PIM Architecture. ISOCC Dongsu Kim, Jongsun Park
2022	J	`jnl`	Early Termination Based Training Acceleration for an Energy-Efficient SNN Processor Design. IEEE Trans. Biomed. Circuits Syst. Sunghyun Choi, Dongwoo Lew, Jongsun Park
2022	—	`conf`	Energy-Efficient STT-MRAM based Digital PIM supporting Vertical Computations Using Sense Amplifier. ISOCC Yeseul Kim, Jongsun Park
2022	—	`conf`	High Detection Rate BCH Code with CRC Code for Memory Application. ISOCC Minseo Kim, Jongsun Park
2022	A	`conf`	Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion. ICCAD Kyeongho Lee, Joonhyung Kim, Jongsun Park
2022	—	`conf`	Percentile Clipping based Low Bit-Precision Quantization for Depth Estimation Network. ISOCC Seungeon Hwang, Jongsun Park
2022	J	`jnl`	SOT-MRAM Digital PIM Architecture With Extended Parallelism in Matrix Multiplication. IEEE Trans. Computers Taehwan Kim, Yunho Jang, Min-Gu Kang, Byong-Guk Park, Kyung-Jin Lee, Jongsun Park
2022	—	`conf`	SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation. ISOCC Hyeyeong Lee, Joonhyung Kim, Jongsun Park
2022	—	`conf`	Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation. ISOCC Taehwan Kim, Jongsun Park
2022	J	`jnl`	Stochastic SOT Device Based SNN Architecture for On-Chip Unsupervised STDP Learning. IEEE Trans. Computers Yunho Jang, Gyuseong Kang, Taehwan Kim, Yeongkyo Seo, Kyung-Jin Lee, Byong-Guk Park, Jongsun Park
2022	—	`conf`	The Quantitative Comparisons of Analog and Digital SRAM Compute-In-Memories for Deep Neural Network Applications. ISOCC Joonhyung Kim, Jongsun Park
2021	J	`jnl`	A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge. IEEE J. Solid State Circuits Kyeongho Lee, Woong Choi, Jongsun Park
2021	A*	`conf`	A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration. DAC Kyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong Choi, Jongsun Park
2021	—	`conf`	A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference. ISOCC Joonhyung Kim, Jongsun Park
2021	B	`conf`	An Energy-Efficient SNN Processor Design based on Sparse Direct Feedback and Spike Prediction. IJCNN Seunghwan Bang, Dongwoo Lew, Sunghyun Choi, Jongsun Park
2021	J	`jnl`	An Error Compensation Technique for Low-Voltage DNN Accelerators. IEEE Trans. Very Large Scale Integr. Syst. Daehan Ji, Dongyeob Shin, Jongsun Park
2021	J	`jnl`	An Even/Odd Error Detection Based Low-Complexity Chase Decoding for Low-Latency RS Decoder Design. IEEE Commun. Lett. Jinho Jeong, Dongyeob Shin, Wongyu Shin, Jongsun Park
2021	J	`jnl`	Exploiting Retraining-Based Mixed-Precision Quantization for Low-Cost DNN Accelerator Design. IEEE Trans. Neural Networks Learn. Syst. Nahsung Kim, Dongyeob Shin, Wonseok Choi, Geonho Kim, Jongsun Park
2021	—	`conf`	Key Length Reconfigurable ARIA Hardware with S-box Optimization. ICEIC Junhyun Song, Junghoon Cho, Jongsun Park
2021	—	`conf`	Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation. ISOCC Hyunchul Park, Jongsun Park
2021	C	`conf`	Low Cost Heterogeneous ARIA S-Box Implementation for CPA-Resistance. ISCAS Junghoon Cho, Junhyun Song, Jongsun Park
2021	C	`conf`	Low Energy Domain Wall Memory Based Convolution Neural Network Design with Optimizing MAC Architecture. ISCAS Jooyoon Kim, Yunho Jang, Taehwan Kim, Jongsun Park
2021	—	`conf`	Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell. ISOCC Dongsu Kim, Jongsun Park
2021	—	`conf`	Low Power SOT-MRAM Cell Configuration For Dual Write Operation. ICEIC Jooyoon Kim, Kwanho Bae, Jongsun Park
2021	—	`conf`	Short Word-Line Pulse with Fast Bit-Line Boosting For High Throughput 6T SRAM-based Compute In-memory Design. ISOCC Minseo Kim, Jongsun Park
2020	—	`conf`	A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance. ISOCC Sungsoo Cheon, Jongsun Park
2020	J	`jnl`	An Energy-Quality Scalable STDP Based Sparse Coding Processor With On-Chip Learning Capability. IEEE Trans. Biomed. Circuits Syst. Heetak Kim, Hoyoung Tang, Woong Choi, Jongsun Park
2020	A*	`conf`	Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. DAC Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park
2020	J	`jnl`	Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. CoRR Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park
2020	—	`conf`	Confidence Score based Mini-batch Skipping for CNN Training on Mini-batch Training Environment. ISOCC Joongho Jo, Jongsun Park
2020	J	`jnl`	Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers. IEEE Access Jinil Chung, Woong Choi, Jongsun Park, Swaroop Ghosh
2020	C	`conf`	Dynamic-Reference Based Early Write Termination for Low Energy SOT-MRAM. ISCAS Taehwan Kim, Eunjong Yeo, Yunho Jang, Yeongkyo Seo, Jongsun Park
2020	—	`conf`	Early Image Termination Technique During STDP Training of Spiking Neural Network. ISOCC Dongwoo Lew, Jongsun Park
2020	—	`conf`	Early Termination of STDP Learning with Spike Counts in Spiking Neural Networks. ISOCC Sunghyun Choi, Jongsun Park
2020	—	`conf`	Efficient TSV Fault Detection Scheme For High Bandwidth Memory Using Pattern Analysis. ISOCC Kwanho Bae, Jongsun Park
2020	—	`conf`	Fast 6T SRAM Bit-Line Computing with Consecutive Short Pulse Word-Lines and Skewed Inverter. ISOCC Jinho Jeong, Jongsun Park
2020	—	`conf`	Implementation of Low Cost ARIA Architecture with Composite Field Optimization and Datapath Modification. ISOCC Junghoon Cho, Junhyun Song, Jongsun Park
2020	—	`conf`	Low Cost Early Exit Decision Unit Design for CNN Accelerator. ISOCC Geonho Kim, Jongsun Park
2020	A*	`conf`	Prediction Confidence based Low Complexity Gradient Computation for Accelerating DNN Training. DAC Dongyeob Shin, Geonho Kim, Joongho Jo, Jongsun Park
2020	J	`jnl`	Rank order coding based spiking convolutional neural network architecture with energy-efficient membrane voltage updates. Neurocomputing Hoyoung Tang, Donghyeon Cho, Dongwoo Lew, Taehwan Kim, Jongsun Park
2020	—	`conf`	Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit. ISOCC Jooyoon Kim, Jongsun Park
2019	J	`jnl`	A Perspective on Test Methodologies for Supervised Machine Learning Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Seyedhamidreza Motaman, Swaroop Ghosh, Jongsun Park
2019	A	`conf`	An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding. ISLPED Heetak Kim, Hoyoung Tang, Jongsun Park
2019	J	`jnl`	Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM. IEEE Trans. Very Large Scale Integr. Syst. Gyuseong Kang, Jongsun Park
2019	J	`jnl`	Compact Implementations of HIGHT Block Cipher on IoT Platforms. Secur. Commun. Networks Bohun Kim, Junghoon Cho, Byungjun Choi, Jongsun Park, Hwajeong Seo
2019	J	`jnl`	Design of Processing-"Inside"-Memory Optimized for DRAM Behaviors. IEEE Access Won Jun Lee, Chang Hyun Kim, Yoonah Paik, Jongsun Park, Il Park, Seon Wook Kim
2019	C	`conf`	Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme. ISCAS Kyeongho Lee, Geon Ko, Jongsun Park
2019	A*	`conf`	Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators. DAC Wonseok Choi, Dongyeob Shin, Jongsun Park, Swaroop Ghosh
2019	J	`jnl`	Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Dongyeob Shin, Wonseok Choi, Jongsun Park, Swaroop Ghosh
2019	J	`jnl`	Spike Counts Based Low Complexity SNN Architecture With Binary Synapse. IEEE Trans. Biomed. Circuits Syst. Hoyoung Tang, Heetak Kim, Hyeonseong Kim, Jongsun Park
2018	J	`jnl`	A Low-Latency and Area-Efficient Gram-Schmidt-Based QRD Architecture for MIMO Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. Dongyeob Shin, Jongsun Park
2018	J	`jnl`	Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions. IEEE Access Byeonggil Park, Jongsun Park, Youngjoo Lee
2018	C	`conf`	Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM. ISCAS Gyuseong Kang, Yunho Jang, Jongsun Park
2018	A*	`conf`	Content addressable memory based binarized neural network accelerator using time-domain signal processing. DAC Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park
2018	J	`jnl`	Energy Efficient Canny Edge Detector for Advanced Mobile Vision Applications. IEEE Trans. Circuits Syst. Video Technol. Juseong Lee, Hoyoung Tang, Jongsun Park
2018	—	`conf`	Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. VLSI Circuits Woong Choi, Jongsun Park, Hoonki Kim, Changnam Park, Taejoong Song
2018	J	`jnl`	Low Cost Convolutional Neural Network Accelerator Based on Bi-Directional Filtering and Bit-Width Reduction. IEEE Access Woong Choi, Kyungrak Choi, Jongsun Park
2018	—	`conf`	Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique. ISOCC Byungjun Choi, Bohun Kim, Jongsun Park
2018	C	`conf`	Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. ISCAS Woong Choi, Kyeongho Lee, Jongsun Park
2018	J	`jnl`	Mosaic-CNN: A Combined Two-Step Zero Prediction Approach to Trade off Accuracy and Computation Energy in Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Cheolhwan Kim, Dongyeob Shin, Bohun Kim, Jongsun Park
2018	B	`conf`	Spike Counts Based Low Complexity Learning with Binary Synapse. IJCNN Hoyoung Tang, Heetak Kim, Donghyeon Cho, Jongsun Park
2018	A	`conf`	Spin Orbit Torque Device based Stochastic Multi-bit Synapses for On-chip STDP Learning. ISLPED Gyuseong Kang, Yunho Jang, Jongsun Park
2018	—	`conf`	Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. ISOCC Taehwan Kim, Jongsun Park
2017	—	`conf`	A DRAM based physical unclonable function capable of generating >10 CICC Qianying Tang, Chen Zhou, Woong Choi, Gyuseong Kang, Jongsun Park, Keshab K. Parhi, Chris H. Kim
2017	J	`jnl`	Adaptive ECC for Tailored Protection of Nanoscale Memory. IEEE Des. Test Dongyeob Shin, Jongsun Park, Jangwon Park, Somnath Paul, Swarup Bhunia
2017	—	`conf`	An efficient convolutional neural networks design with heterogeneous SRAM cell sizing. ISOCC Wonseok Choi, Jongsun Park
2017	A	`conf`	Bit-width reduction and customized register for low cost convolutional neural network accelerator. ISLPED Kyungrak Choi, Woong Choi, Kyungho Shin, Jongsun Park
2017	J	`jnl`	Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design. IEEE Trans. Very Large Scale Integr. Syst. Gyuseong Kang, Woong Choi, Jongsun Park
2017	J	`jnl`	Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. Kyungho Shin, Woong Choi, Jongsun Park
2017	J	`jnl`	Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Woong Choi, Jongsun Park
2017	J	`jnl`	Novel Folded-KES Architecture for High-Speed and Area-Efficient BCH Decoders. IEEE Trans. Circuits Syst. II Express Briefs Byeonggil Park, Seungyong An, Jongsun Park, Youngjoo Lee
2017	J	`jnl`	Replacing eFlash with STTRAM in IoTs: Security Challenges and Solutions. J. Hardw. Syst. Secur. Asmit De, Mohammad Nasim Imtiaz Khan, Jongsun Park, Swaroop Ghosh
2016	J	`jnl`	A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator. IEEE Trans. Very Large Scale Integr. Syst. Chan-Keun Kwon, Hoon Ki Kim, Jongsun Park, Soo-Won Kim
2016	J	`jnl`	A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design. IEEE Trans. Circuits Syst. I Regul. Pap. Woong Choi, Jongsun Park
2016	—	`conf`	A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method. APCCAS Gihoon Jung, Kyungrak Choi, Jongsun Park
2016	—	`conf`	Customized SRAM design for low power video code applications. ISOCC Sangkyu Lee, Hoyoung Tang, Kyungrak Choi, Jongsun Park
2016	A	`conf`	Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency. ISLPED Jinil Chung, Jongsun Park, Swaroop Ghosh
2016	J	`jnl`	Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design. IEEE Trans. Circuits Syst. I Regul. Pap. Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh
2016	J	`jnl`	Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar
2016	J	`jnl`	Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors. IEEE Trans. Very Large Scale Integr. Syst. Hoyoung Tang, Jongsun Park
2016	J	`jnl`	Wearables, Implants, and Internet of Things: The Technology Needs in the Evolving Landscape. IEEE Trans. Multi Scale Comput. Syst. Sandip Ray, Jongsun Park, Swarup Bhunia
2015	J	`jnl`	A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder. IEEE J. Solid State Circuits Woong Choi, Gyuseong Kang, Jongsun Park
2015	C	`conf`	A hybrid multimode BCH encoder architecture for area efficient re-encoding approach. ISCAS Hoyoung Tang, Gihoon Jung, Jongsun Park
2015	J	`jnl`	D Microprocess. Microsystems Joon Goo Lee, Seon Wook Kim, Dong-Hyun Kim, Younga Cho, Jae-Sung Rieh, Gyusung Kang, Jongsun Park, Hokyu Lee, Sejin Park, Chulwoo Kim
2015	A*	`conf`	Domain wall memory based digital signal processors for area and energy-efficiency. DAC Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh
2015	J	`jnl`	Guest Editors' Introduction: Wearables, Implants, and Internet of Things. IEEE Trans. Multi Scale Comput. Syst. Sandip Ray, Jongsun Park, Swarup Bhunia
2015	A*	`conf`	Self-correcting STTRAM under magnetic field attacks. DAC Jae-Won Jang, Jongsun Park, Swaroop Ghosh, Swarup Bhunia
2014	C	`conf`	A low-complexity composite QR decomposition architecture for MIMO detector. ISCAS Ji-Hwan Yoon, Dongyeob Shin, Jongsun Park
2014	J	`jnl`	An Efficient Memory-Address Remapping Technique for High-Throughput QC-LDPC Decoder. Circuits Syst. Signal Process. Ji-Hwan Yoon, Jongsun Park
2014	J	`jnl`	Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks. IEEE Trans. Very Large Scale Integr. Syst. Anandaroop Ghosh, Somnath Paul, Jongsun Park, Swarup Bhunia
2014	J	`jnl`	Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority. IEEE Trans. Very Large Scale Integr. Syst. Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park
2014	J	`jnl`	VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications. IEEE Trans. Circuits Syst. II Express Briefs Jangwon Park, Jongsun Park, Swarup Bhunia
2013	J	`jnl`	Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip. IEEE Trans. Very Large Scale Integr. Syst. Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim
2013	J	`jnl`	Design of Wavelet-Based ECG Detector for Implantable Cardiac Pacemakers. IEEE Trans. Biomed. Circuits Syst. Young-Jae Min, Hoon Ki Kim, Yu-Ri Kang, Gil-Su Kim, Jongsun Park, Soo-Won Kim
2013	C	`conf`	Multidimensional Householder based high-speed QR decomposition architecture for MIMO receivers. ISCAS Iput Heri Kurniawan, Ji-Hwan Yoon, Jongsun Park
2013	J	`jnl`	Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System. J. Signal Process. Syst. Insoo Lee, Jinmo Kwon, Jangwon Park, Jongsun Park
2013	—	`conf`	Reconfigurable ECC for adaptive protection of memory. MWSCAS Abhishek Basak, Somnath Paul, Jangwon Park, Jongsun Park, Swarup Bhunia
2012	J	`jnl`	Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics. IEEE Trans. Circuits Syst. II Express Briefs Woojin Rim, Woong Choi, Jongsun Park
2012	J	`jnl`	Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. Phi-Hung Pham, Jongsun Park, Phuong Mau, Chulwoo Kim
2012	C	`conf`	Dual queue based rate selecting schedule for throughput enhancement in WLANs. ISCAS Dongwan Kim, Wan-Seon Lim, Jongsun Park
2012	J	`jnl`	Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Jinmo Kwon, Ik Joon Chang, Insoo Lee, Heemin Park, Jongsun Park
2012	C	`conf`	High-speed tournament givens rotation-based QR Decomposition Architecture for MIMO Receiver. ISCAS Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park
2012	J	`jnl`	Resource Efficient Implementation of Low Power MB-OFDM PHY Baseband Modem With Highly Parallel Architecture. IEEE Trans. Very Large Scale Integr. Syst. Seokjoong Hwang, Youngsun Han, Seon Wook Kim, Jongsun Park, Byung Gueon Min
2011	J	`jnl`	A Jitter and Power Analysis on DCO. IEEE Trans. Circuits Syst. II Express Briefs Doo-Chan Lee, Kyu-Young Kim, Young-Jae Min, Jongsun Park, Soo-Won Kim
2011	J	`jnl`	A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption. IEEE Trans. Very Large Scale Integr. Syst. Seok-Jae Lee, Ji-Woong Choi, Seon Wook Kim, Jongsun Park
2011	J	`jnl`	An Energy Efficient V IEEE J. Solid State Circuits Kyu-Young Kim, Yonghwan Kim, Doo-Chan Lee, Yu-Ri Kang, Hoon Ki Kim, Soo-Won Kim, Jongsun Park
2011	—	`conf`	Improved MIMO SIC Detection Exploiting ML Criterion. VTC Fall Ji-Woong Choi, Jungwon Lee, Hui-Ling Lou, Jongsun Park
2011	J	`jnl`	Low-power programmable divider with a shared counter for frequency synthesiser. IET Circuits Devices Syst. Kyu-Young Kim, Young-Jae Min, Soo-Won Kim, Jongsun Park
2010	J	`jnl`	Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy. IEEE Trans. Very Large Scale Integr. Syst. Jongsun Park, Jung Hwan Choi, Kaushik Roy
2010	J	`jnl`	Energy Efficient Hardware Architecture of LU Triangularization for MIMO Receiver. IEEE Trans. Circuits Syst. II Express Briefs Ji-Woong Choi, Jungwon Lee, Byung Gueon Min, Jongsun Park
2010	J	`jnl`	Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. J. Signal Process. Syst. Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy
2010	J	`jnl`	Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling. IET Circuits Devices Syst. Ik Joon Chang, Jongsun Park, Kunhyuk Kang, Kaushik Roy
2010	J	`jnl`	Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories. Microelectron. Reliab. Hee-Dong Kim, Ho-Myoung An, Yujeong Seo, Yongjie Zhang, Jongsun Park, Tae Geun Kim
2010	J	`jnl`	ProMINoC: An efficient Network-on-Chip design for flexible data permutation. IEICE Electron. Express Phi-Hung Pham, Jongsun Park, Chulwoo Kim
2009	J	`jnl`	A distributed MAC design for data collision-free wireless USB home networks. IEEE Trans. Consumer Electron. Jin-Woo Kim, Kyeong Hur, Jongsun Park, Doo Seop Eom
2009	J	`jnl`	A fair distributed resource allocation method in UWB wireless PANs with WiMedia MAC. J. Commun. Networks Seokhwan Kim, Kyeong Hur, Jongsun Park, Doo Seop Eom, Kwang-il Hwang
2009	J	`jnl`	A packet forwarding controller for mobile IP-based networks with packet buffering. IEEE Trans. Consumer Electron. Seung Beom Lee, Kyeong Hur, Jongsun Park, Doo Seop Eom
2009	J	`jnl`	Enhancing Location Estimation and Reducing Computation using Adaptive Zone Based K-NNSS Algorithm. KSII Trans. Internet Inf. Syst. Sung-Hak Song, Chang-Hoon Lee, Ju-Hyun Park, Kyo-Jun Koo, Jong-Kook Kim, Jongsun Park
2009	J	`jnl`	Soft MIMO ML demodulation based on bitwise constellation partitioning. IEEE Commun. Lett. Jungwon Lee, Ji-Woong Choi, Hui-Ling Lou, Jongsun Park
2008	J	`jnl`	A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption. J. Signal Process. Syst. Jongsun Park, Kaushik Roy
2006	A	`conf`	Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. DATE Jongsun Park, Jung Hwan Choi, Kaushik Roy
2006	J	`jnl`	Efficient modeling of 1/f IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jongsun Park, Khurram Muhammad, Kaushik Roy
2004	—	`conf`	A low power reconfigurable DCT architecture to trade off image quality for computational complexity. ICASSP (5) Jongsun Park, Kaushik Roy
2004	J	`jnl`	Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid State Circuits Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy
2004	—	`conf`	Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. ICASSP (5) Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy
2003	—	`conf`	Efficient generation of 1/f CICC Jongsun Park, Khurram Muhammad, Kaushik Roy
2003	J	`jnl`	High-performance FIR filter design based on sharing multiplication. IEEE Trans. Very Large Scale Integr. Syst. Jongsun Park, Khurram Muhammad, Kaushik Roy
2002	A	`conf`	High performance and low power FIR filter design based on sharing multiplication. ISLPED Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy
2002	Misc	`conf`	Low power reconfigurable DCT design based on sharing multiplication. ICASSP Jongsun Park, Soonkeon Kwon, Kaushik Roy
2000	Misc	`conf`	Non-adaptive and adaptive filter implementation based on sharing multiplication. ICASSP Jongsun Park, Hunsoo Choo, Khurram Muhammad, Seung Hoon Choi, Yonghee Im, Kaushik Roy