Jong-Hyeok Yoon

40 papers A* 1A 2C 1Journal 17Unranked 19

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	34.5 A 0.0523mm ISSCC Jihun Son, Minsu Park, Chansoo Park, Kyoungtae Lee, Jong-Hyeok Yoon, Junghyup Lee, Minyoung Song
2026	—	`conf`	36.5 A 185.6dB-FOMDR 180.3dB-FOMSNDR 10.64-NEF NS-SAR-ADC with Calibration-Free 2 ISSCC Geunha Kim, Kyuhyeon Park, Minoo Lee, Jeongyoon Wie, Seokhan Jeong, YeonJae Shin, Kyoungtae Lee, Jong-Hyeok Yoon, Minyoung Song, Junghyup Lee
2026	J	`jnl`	Design and Analysis of ΔΣ Modulator Analogous Bang-Bang Digital PLL. Int. J. Circuit Theory Appl. Minsu Park, Jong-Hyeok Yoon, Minyoung Song
2025	J	`jnl`	An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. IEEE J. Solid State Circuits Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2025	J	`jnl`	BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. IEEE J. Solid State Circuits Jaehyun Lee, Dong-gu Choi, Gain Kim, Minyoung Song, Jong-Hyeok Yoon
2025	A	`conf`	CAM-CIM: A Hybrid Compute-in-Memory Using Content-Addressable Memory with Subword Split Mapping for Reduced ADC Resolution. ISLPED Sangwoo Jung, Hojin Lee, Yejin Lee, Jiyong Park, Dahoon Park, Hyunseob Shin, Jong-Hyeok Yoon, Jaeha Kung
2024	—	`conf`	30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024	—	`conf`	A 65nm 687.5-TOPS/W Drive Strength-based SRAM Compute-In-Memory Macro with Adaptive Dynamic Range for Edge AI applications. A-SSCC Dong-gu Choi, Jaehyun Lee, Jahyun Koo, Woo Kyoung Han, Dahoon Park, Jaeha Kung, Junghyup Lee, Jong-Hyeok Yoon
2024	—	`conf`	A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO-ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition. VLSI Technology and Circuits Sehwan Lee, Taeryoung Seol, Geunha Kim, Minyoung Song, Gain Kim, Jong-Hyeok Yoon, Arup K. George, Junghyup Lee
2024	J	`jnl`	A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC. IEEE Trans. Circuits Syst. II Express Briefs Jaewon Lee, Seoyoung Jang, DongGeon Kim, Yujin Choi, Jong-Hyeok Yoon, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024	J	`jnl`	A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous Processing-in-Memory Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Sangwoo Jung, Jaehyun Lee, Dahoon Park, Youngjoo Lee, Jong-Hyeok Yoon, Jaeha Kung
2024	—	`conf`	BEE-SLAM: A 65nm 17.96 TOPS/W 97.55%-Sparse-Activity Hybrid Mixed-Signal/Digital Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. CICC Jaehyun Lee, Dong-gu Choi, Minyoung Song, Gain Kim, Jong-Hyeok Yoon
2023	—	`conf`	A 1V-Supply $1.85\mathrm{V}_{\text{PP}}$ -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2 ISSCC Geunha Kim, Sehwan Lee, Taeryoung Seol, Seungyeob Baik, YeonJae Shin, Gain Kim, Jong-Hyeok Yoon, Arup K. George, Junghyup Lee
2023	—	`conf`	A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC. ISOCC Seongyeon Yu, Namwook Hur, Wansun Kim, Mann-Ho Cho, Hyunchul Sohn, Joonki Suh, Hongsik Jeong, Jong-Hyeok Yoon
2022	J	`jnl`	A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. IEEE J. Solid State Circuits Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022	J	`jnl`	A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. IEEE J. Solid State Circuits Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2022	—	`conf`	A Neuromorphic SLAM Accelerator Supporting Multi-Agent Error Correction in Swarm Robotics. ISOCC Jaehyun Lee, Jong-Hyeok Yoon
2022	J	`jnl`	BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory. IEEE Trans. Circuits Syst. I Regul. Pap. Foroozan Karimzadeh, Jong-Hyeok Yoon, Arijit Raychowdhury
2022	C	`conf`	Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory. ISCAS Brian Crafton, Connor Talley, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury
2022	—	`conf`	DualPIM: A Dual-Precision and Low-Power CNN Inference Engine Using SRAM- and eDRAM-based Processing-in-Memory Arrays. AICAS Sangwoo Jung, Jaehyun Lee, Huiseong Noh, Jong-Hyeok Yoon, Jaeha Kung
2022	A*	`conf`	Improving compute in-memory ECC reliability with successive correction. DAC Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
2021	—	`conf`	29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. ISSCC Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021	—	`conf`	A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. CICC Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2021	—	`conf`	CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation. A-SSCC Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury
2021	J	`jnl`	NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics. IEEE J. Solid State Circuits Jong-Hyeok Yoon, Arijit Raychowdhury
2021	A	`conf`	Statistical Optimization of Compute In-Memory Performance Under Device Variation. ISLPED Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Arijit Raychowdhury
2020	J	`jnl`	3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jong-Hyeok Yoon, Kyeongha Kwon, Hyeon-Min Bae
2020	—	`conf`	31.1 A 65nm 8.79TOPS/W 23.82mW Mixed-Signal Oscillator-Based NeuroSLAM Accelerator for Applications in Edge Robotics. ISSCC Jong-Hyeok Yoon, Arijit Raychowdhury
2020	J	`jnl`	A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links. IEEE Trans. Circuits Syst. I Regul. Pap. Sejun Jeon, Woohyun Kwon, Jong-Hyeok Yoon, Taehun Yoon, Kyeongha Kwon, Jaehyeok Yang, Hyeon-Min Bae
2019	J	`jnl`	An Electronic Dispersion Compensation Transceiver for 10- and 28-Gb/s Directly Modulated Lasers-Based Optical Links. IEEE J. Solid State Circuits Kyeongha Kwon, Jong-Hyeok Yoon, Younho Jeon, Hanho Choi, Sejun Jeon, Hyeon-Min Bae
2018	—	`conf`	A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS. ISSCC Sejun Jeon, Woohyun Kwon, Taehun Yoon, Jong-Hyeok Yoon, Kyeongha Kwon, Jaehyeok Yang, Hyeon-Min Bae
2018	—	`conf`	A 28Gb/s transceiver with chirp-managed EDC for DML systems. ISSCC Kyeongha Kwon, Jong-Hyeok Yoon, Hanho Choi, Younho Jeon, Jaehyeok Yang, Bongjin Kim, Soon-Won Kwon, Minsik Kim, Sejun Jeon, Hyosup Won, Hyeon-Min Bae
2018	—	`conf`	A 3.125-to-28.125 Gb/s multi-standard transceiver with a fully channel-independent operation in 40nm CMOS. CICC Jong-Hyeok Yoon, Kyeongha Kwon, Hyeon-Min Bae
2017	J	`jnl`	A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single LC VCO in 90 nm CMOS. IEEE J. Solid State Circuits Jong-Hyeok Yoon, Soon-Won Kwon, Hyeon-Min Bae
2016	J	`jnl`	A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Joon-Yeong Lee, Jaehyeok Yang, Jong-Hyeok Yoon, Soon-Won Kwon, Hyosup Won, Jinho Han, Hyeon-Min Bae
2015	J	`jnl`	A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS. IEEE J. Solid State Circuits Hyosup Won, Taehun Yoon, Jinho Han, Joon-Yeong Lee, Jong-Hyeok Yoon, Taeho Kim, Jeong-Sup Lee, Sangeun Lee, Kwangseok Han, Jinhee Lee, Jinho Park, Hyeon-Min Bae
2015	J	`jnl`	A 6 Gb/s Transceiver With a Nonlinear Electronic Dispersion Compensator for Directly Modulated Distributed-Feedback Lasers. IEEE J. Solid State Circuits Kyeongha Kwon, Jong-Hyeok Yoon, Hyeon-Min Bae
2015	—	`conf`	A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS. CICC Jong-Hyeok Yoon, Soon-Won Kwon, Hyeon-Min Bae
2014	—	`conf`	8.1 A 6Gb/s transceiver with a nonlinear electronic dispersion compensator for directly modulated distributed-feedback lasers. ISSCC Kyeongha Kwon, Jong-Hyeok Yoon, Soon-Won Kwon, Jaehyeok Yang, Joon-Yeong Lee, Hyosup Won, Hyeon-Min Bae
2014	J	`jnl`	A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links. IEEE Trans. Circuits Syst. I Regul. Pap. Joon-Yeong Lee, Jong-Hyeok Yoon, Hyeon-Min Bae