Jonathan W. Greene

18 papers A* 1A 9B 1Journal 5Unranked 2

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models. ISQED Gabriel Barajas, Jonathan W. Greene, Fei Li, James Tandon
2023	A	`conf`	FPGA Mux Usage and Routability Estimates without Explicit Routing. FPGA Jonathan W. Greene
2023	A	`conf`	Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. DATE Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek
2018	A	`conf`	Improving FPGA Performance with a S44 LUT Structure. FPGA Wenyi Feng, Jonathan W. Greene, Alan Mishchenko
2017	A	`ed.`	Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017 FPGA Jonathan W. Greene, Jason Helge Anderson
2016	A	`ed.`	Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016 FPGA Deming Chen, Jonathan W. Greene
2015	A	`conf`	Technology Mapping into General Programmable Cells. FPGA Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene
2014	A	`conf`	Rent's rule based FPGA packing for routability optimization. FPGA Wenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner, Arun Kundu
2011	A	`conf`	A 65nm flash-based FPGA fabric optimized for low cost and power. FPGA Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner
2009	J	`jnl`	Improving Simulated Annealing-Based FPGA Placement With Directed Moves. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene
2007	B	`conf`	Improving Annealing Via Directed Moves. FPL Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene, Doris T. Chen
2007	J	`jnl`	Post-Placement Interconnect Entropy. IEEE Trans. Very Large Scale Integr. Syst. Wenyi Feng, Jonathan W. Greene
2006	A	`conf`	Post-placement interconnect entropy. FPGA Wenyi Feng, Jonathan W. Greene
2006	—	`conf`	Post-placement interconnect entropy: how many configuration bits does a programmable logic device need? SLIP Wenyi Feng, Jonathan W. Greene
1993	J	`jnl`	Segmented channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vwani P. Roychowdhury, Jonathan W. Greene, Abbas El Gamal
1990	A*	`conf`	Segmented Channel Routing. DAC Jonathan W. Greene, Vwani P. Roychowdhury, Sinan Kaptanoglu, Abbas El Gamal
1989	J	`jnl`	An architecture for electrically configurable gate arrays. IEEE J. Solid State Circuits Abbas El Gamal, Jonathan W. Greene, Justin Reyneri, Eric Rogoyski, Khaled A. El-Ayat, Amr Mohsen
1984	J	`jnl`	Configuration of VLSI Arrays in the Presence of Defects. J. ACM Jonathan W. Greene, Abbas El Gamal