Jonathan Rose - RankMe

144 papers A* 9A 46B 9C 1Misc 6Journal 46Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Fully Generative Motivational Interviewing Counsellor Chatbot for Moving Smokers Towards the Decision to Quit. ACL (Findings) Zafarullah Mahmood, Soliman Ali, Jiading Zhu, Mohamed Abdelwahab, Michelle Yu Collins, Sihan Chen, Yi Cheng Zhao, Jodi Wolff, Osnat C. Melamed, Nadia Minian, Marta Maslej, Carolynne Cooper, Matt Ratto, Peter Selby, Jonathan Rose
2025	J	`jnl`	A Fully Generative Motivational Interviewing Counsellor Chatbot for Moving Smokers Towards the Decision to Quit. CoRR Zafarullah Mahmood, Soliman Ali, Jiading Zhu, Mohamed Abdelwahab, Michelle Yu Collins, Sihan Chen, Yi Cheng Zhao, Jodi Wolff, Osnat Melamed, Nadia Minian, Marta Maslej, Carolynne Cooper, Matt Ratto, Peter Selby, Jonathan Rose
2024	—	`conf`	Generation, Distillation and Evaluation of Motivational Interviewing-Style Reflections with a Foundational Language Model. EACL (1) Andrew Brown, Jiading Zhu, Mohamed Abdelwahab, Alec Dong, Cindy Wang, Jonathan Rose
2024	J	`jnl`	Generation, Distillation and Evaluation of Motivational Interviewing-Style Reflections with a Foundational Language Model. CoRR Andrew Brown, Jiading Zhu, Mohamed Abdelwahab, Alec Dong, Cindy Wang, Jonathan Rose
2024	J	`jnl`	Plug and Play with Prompts: A Prompt Tuning Approach for Controlling Text Generation. CoRR Rohan Deepak Ajwani, Zining Zhu, Jonathan Rose, Frank Rudzicz
2020	B	`conf`	Detection and Correspondence Matching of Corneal Reflections for Eye Tracking Using Deep Learning. ICPR Soumil Chugh, Braiden Brousseau, Jonathan Rose, Moshe Eizenman
2020	J	`jnl`	Hybrid Eye-Tracking on a Smartphone with CNN Feature Extraction and an Infrared 3D Model. Sensors Braiden Brousseau, Jonathan Rose, Moshe Eizenman
2020	J	`jnl`	Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2018	B	`conf`	Automatic Topology Optimization for FPGA Interconnect Synthesis. FPL Alex Rodionov, Jonathan Rose
2018	J	`jnl`	High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. ACM Trans. Reconfigurable Technol. Syst. Henry Wong, Vaughn Betz, Jonathan Rose
2018	—	`conf`	SmartEye: An Accurate Infrared Eye Tracking System for Smartphones. UEMCON Braiden Brousseau, Jonathan Rose, Moshe Eizenman
2017	—	`conf`	Energy efficient object detection on the mobile GP-GPU. AFRICON Fitsum Assamnew Andargie, Jonathan Rose, Todd M. Austin, Valeria Bertacco
2017	A	`conf`	Synchronization Constraints for Interconnect Synthesis. FPGA Alex Rodionov, Jonathan Rose
2016	J	`jnl`	Fine-Grained Interconnect Synthesis. ACM Trans. Reconfigurable Technol. Syst. Alex Rodionov, David Biancolin, Jonathan Rose
2016	Misc	`conf`	High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors. FCCM Henry Wong, Vaughn Betz, Jonathan Rose
2016	J	`jnl`	Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. ACM Trans. Reconfigurable Technol. Syst. Henry Wong, Vaughn Betz, Jonathan Rose
2015	—	`conf`	Automatic FPGA system and interconnect construction with multicast and customizable topology. FPT Alex Rodionov, Jonathan Rose
2015	A	`conf`	Fine-Grained Interconnect Synthesis. FPGA Alex Rodionov, David Biancolin, Jonathan Rose
2015	—	`conf`	Performance characterization of mobile GP-GPUs. AFRICON Fitsum Assamnew Andargie, Jonathan Rose
2014	Misc	`conf`	On Hard Adders and Carry Chains in FPGAs. FCCM Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2014	J	`jnl`	Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design. IEEE Trans. Very Large Scale Integr. Syst. Henry Wong, Vaughn Betz, Jonathan Rose
2014	A	`conf`	Towards interconnect-adaptive packing for FPGAs. FPGA Jason Luu, Jonathan Rose, Jason Helge Anderson
2014	J	`jnl`	VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2013	—	`conf`	Efficient methods for out-of-order load/store execution for high-performance soft processors. FPT Henry Wong, Vaughn Betz, Jonathan Rose
2012	—	`conf`	An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detection. FPT Braiden Brousseau, Jonathan Rose
2012	B	`conf`	On the difficulty of pin-to-wire routing in FPGAs. FPL Niyati Shah, Jonathan Rose
2012	J	`jnl`	Portable and scalable FPGA-based acceleration of a direct linear system solver. ACM Trans. Reconfigurable Technol. Syst. Wei Zhang, Vaughn Betz, Jonathan Rose
2012	J	`jnl`	Portable, Flexible, and Scalable Soft Vector Processors. IEEE Trans. Very Large Scale Integr. Syst. Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2012	A	`conf`	The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson
2011	J	`jnl`	A new, fast algorithm for detecting protein coevolution using maximum compatible cliques. Algorithms Mol. Biol. Alex Rodionov, Alexandr Bezginov, Jonathan Rose, Elisabeth R. M. Tillier
2011	A	`conf`	Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. FPGA Jason Luu, Jason Helge Anderson, Jonathan Rose
2011	A	`conf`	Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. FPGA Henry Wong, Vaughn Betz, Jonathan Rose
2011	J	`jnl`	Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design. IEEE Trans. Very Large Scale Integr. Syst. Ian Kuon, Jonathan Rose
2011	A	`conf`	The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. FPGA Jonathan Rose, Guy G. Lemieux
2011	J	`jnl`	VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. ACM Trans. Reconfigurable Technol. Syst. Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Kenneth B. Kent, Jonathan Rose
2010	J	`jnl`	Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters. IEEE Trans. Very Large Scale Integr. Syst. Peter A. Jamieson, Jonathan Rose
2010	—	`conf`	Faster coevolution detection of proteins using maximum similar cliques. BCB Alex Rodionov, Alexandr Bezginov, Jonathan Rose, Elisabeth R. M. Tillier
2009	B	`conf`	Data parallel FPGA workloads: Software versus hardware. FPL Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2009	Misc	`conf`	FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. FCCM Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose
2009	Misc	`conf`	Fine-grain performance scaling of soft vector processors. CASES Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2009	A	`conf`	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. FPGA Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2009	B	`conf`	The evolution of architecture exploration of programmable devices. FPL Jonathan Rose
2009	A	`conf`	VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. FPGA Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose
2008	A	`conf`	Area and delay trade-offs in the circuit and architecture design of FPGAs. FPGA Ian Kuon, Jonathan Rose
2008	A*	`conf`	Automated transistor sizing for FPGA architecture exploration. DAC Ian Kuon, Jonathan Rose
2008	A	`conf`	Modeling routing demand for early-stage FPGA architecture development. FPGA Wei Mark Fang, Jonathan Rose
2008	—	`conf`	Portable and scalable FPGA-based acceleration of a direct linear system solver. FPT Wei Zhang, Vaughn Betz, Jonathan Rose
2008	Misc	`conf`	VESPA: portable, scalable, and flexible FPGA-based vector processors. CASES Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2007	—	`conf`	Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters. FPT Peter Jamieson, Jonathan Rose
2007	J	`jnl`	Exploration and Customization of FPGA-Based Soft Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2007	J	`jnl`	FPGA Architecture: Survey and Challenges. Found. Trends Electron. Des. Autom. Ian Kuon, Russell Tessier, Jonathan Rose
2007	J	`jnl`	Measuring the Gap Between FPGAs and ASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ian Kuon, Jonathan Rose
2006	A	`conf`	Application-specific customization of soft processor microarchitecture. FPGA Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2006	—	`conf`	Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters. FPT Peter Jamieson, Jonathan Rose
2006	—	`conf`	Invited Keynote 1: Closing the gap between FPGAs and ASICs. FPT Jonathan Rose
2006	A	`conf`	Measuring the gap between FPGAs and ASICs. FPGA Ian Kuon, Jonathan Rose
2006	J	`jnl`	Reconfigurable hardware implementation of a phase-correlation stereoalgorithm. Mach. Vis. Appl. Ahmad Darabiha, W. James MacLean, Jonathan Rose
2006	J	`jnl`	Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits. IEEE Trans. Very Large Scale Integr. Syst. Andy Gean Ye, Jonathan Rose
2005	B	`conf`	A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. FPL Peter Jamieson, Jonathan Rose
2005	A	`conf`	Design, layout and verification of an FPGA using automated tools. FPGA Ian Kuon, Aaron Egier, Jonathan Rose
2005	B	`conf`	Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. FPL Andy Gean Ye, Jonathan Rose
2005	A	`conf`	The Stratix II logic and routing architecture. FPGA David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose
2005	—	`conf`	The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth. FPT Joshua Fender, Jonathan Rose, David R. Galloway
2005	Misc	`conf`	The microarchitecture of FPGA-based soft processors. CASES Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan
2005	A	`conf`	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. FPGA Andy Gean Ye, Jonathan Rose
2004	A	`conf`	A synthesis oriented omniscient manual editor. FPGA Tomasz S. Czajkowski, Jonathan Rose
2004	—	`conf`	Hard vs. Soft: The Central Question of Pre-Fabricated Silicon. ISMVL Jonathan Rose
2004	B	`conf`	Hardware Accelerated Novel Protein Identification. FPL Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher W. V. Hogue
2004	J	`jnl`	Synthetic circuit generation using clustering and iteration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Paul D. Kundarewich, Jonathan Rose
2004	J	`jnl`	The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Trans. Very Large Scale Integr. Syst. Elias Ahmed, Jonathan Rose
2004	A	`conf`	Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. FPGA Ian Kuon, Aaron Egier, Jonathan Rose
2004	—	`conf`	Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits. FPT Andy Gean Ye, Jonathan Rose
2003	—	`conf`	A high-speed ray tracing engine built on a field-programmable system. FPT Joshua Fender, Jonathan Rose
2003	—	`conf`	A parameterized automatic cache generator for FPGAs. FPT Peter Yiannacouras, Jonathan Rose
2003	—	`conf`	Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. CICC Andy Gean Ye, Jonathan Rose, David M. Lewis
2003	A	`conf`	Automatic transistor and physical design of FPGA tiles from an architectural specification. FPGA Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose
2003	A	`conf`	Synthetic circuit generation using clustering and iteration. FPGA Paul D. Kundarewich, Jonathan Rose
2003	A	`conf`	The Stratix FPGA David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose
2003	—	`conf`	Video-Rate Stereo Depth Measurement on Programmable Hardware. CVPR (1) Ahmad Darabiha, Jonathan Rose, W. James MacLean
2002	J	`jnl`	Automatic generation of synthetic sequential benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael D. Hutton, Jonathan Rose, Derek G. Corneil
2002	A	`conf`	EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. FPGA William Chow, Jonathan Rose
2002	—	`conf`	Nearest neighbour interconnect architecture in deep submicron FPGAs. CICC Ajay Roopchansingh, Jonathan Rose
2002	—	`conf`	Synthesizing datapath circuits for FPGAs with emphasis on area minimization. FPT Andy Gean Ye, Jonathan Rose, David M. Lewis
2001	A	`conf`	Mixing buffers and pass transistors in FPGA routing architectures. FPGA Mike Sheng, Jonathan Rose
2001	A*	`conf`	Panel: (When) Will FPGAs Kill ASICs? DAC Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
2001	J	`jnl`	Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. Very Large Scale Integr. Syst. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
2000	J	`jnl`	A novel and efficient routing architecture for multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. Mohammed A. S. Khalid, Jonathan Rose
2000	A	`conf`	Automatic generation of FPGA routing architectures from high-level descriptions. FPGA Vaughn Betz, Jonathan Rose
2000	A	`conf`	Real-time, frame-rate face detection on a configurable hardware system (poster abstract). FPGA Rob McCready, Jonathan Rose
2000	J	`jnl`	Speed and area tradeoffs in cluster-based FPGA architectures. IEEE Trans. Very Large Scale Integr. Syst. Alexander Marquardt, Vaughn Betz, Jonathan Rose
2000	A	`conf`	The effect of LUT and cluster size on deep-submicron FPGA performance and density. FPGA Elias Ahmed, Jonathan Rose
2000	A	`conf`	Timing-driven placement for FPGAs. FPGA Alexander Marquardt, Vaughn Betz, Jonathan Rose
1999	—	`conf`	Applications of clone circuits to issues in physical-design. ISCAS (6) Michael D. Hutton, Jonathan Rose
1999	—	`book`	Architecture and CAD for Deep-Submicron FPGAS Vaughn Betz, Jonathan Rose, Alexander Marquardt
1999	—	`conf`	Equivalence classes of clone circuits for physical-design benchmarking. ISCAS (6) Michael D. Hutton, Jonathan Rose
1999	A	`conf`	FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. FPGA Vaughn Betz, Jonathan Rose
1999	—	`conf`	Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems. IPPS/SPDP Workshops Mohammed A. S. Khalid, Jonathan Rose
1999	J	`jnl`	The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout. IEEE Trans. Very Large Scale Integr. Syst. Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja
1999	J	`jnl`	The design of an SRAM-based field-programmable gate array. I. Architecture. IEEE Trans. Very Large Scale Integr. Syst. Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja
1999	J	`jnl`	The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. Very Large Scale Integr. Syst. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
1999	A	`conf`	Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs. FPGA Yaska Sankar, Jonathan Rose
1999	A	`conf`	Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. FPGA Alexander Marquardt, Vaughn Betz, Jonathan Rose
1998	A	`conf`	A Fast Routability-Driven Router for FPGAs. FPGA Jordan S. Swartz, Vaughn Betz, Jonathan Rose
1998	A	`conf`	A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. FPGA Mohammed A. S. Khalid, Jonathan Rose
1998	J	`jnl`	Characterization and parameterized generation of synthetic combinational benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil
1998	A	`conf`	Constraints from Hell: How to Tell Makes a Good FPGA (Panel). FPGA Jonathan Rose, Sinan Kaptanoglu, Clive McCarthy, Rob Smith, Sandip Vij, Steve Taylor
1998	J	`jnl`	Effect of the prefabricated routing track distribution on FPGA area-efficiency. IEEE Trans. Very Large Scale Integr. Syst. Vaughn Betz, Jonathan Rose
1998	J	`jnl`	How Much Logic Should Go in an FPGA Logic Block? IEEE Des. Test Comput. Vaughn Betz, Jonathan Rose
1998	J	`jnl`	The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. Very Large Scale Integr. Syst. David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
1997	A	`conf`	Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond. FPGA Jonathan Rose, Dwight D. Hill
1997	A	`conf`	Generation of Synthetic Sequential Benchmark Circuits. FPGA Michael D. Hutton, Jonathan Rose, Derek G. Corneil
1997	A	`conf`	Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
1997	A	`conf`	The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
1997	B	`conf`	VPR: A new packing, placement and routing tool for FPGA research. FPL Vaughn Betz, Jonathan Rose
1996	A*	`conf`	Characterization and Parameterized Random Generation of Digital Circuits. DAC Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil
1996	A	`conf`	Directional bias and non-uniformity in FPGA global routing architectures. ICCAD Vaughn Betz, Jonathan Rose
1996	J	`jnl`	FPGA and CPLD Architectures: A Tutorial. IEEE Des. Test Comput. Stephen Brown, Jonathan Rose
1996	A	`ed.`	Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, FPGA 1996, Monterey, CA, USA, February 11-13, 1996 FPGA Jonathan Rose, Carl Ebeling
1995	A	`conf`	Architecture of Centralized Field-Configurable Memory. FPGA Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
1995	A	`ed.`	Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995 FPGA Pak K. Chan, Jonathan Rose
1995	A	`conf`	Using Architectural "Families" to Increase FPGA Speed and Density. FPGA Vaughn Betz, Jonathan Rose
1994	A	`conf`	Definition and solution of the memory packing problem for field-programmable systems. ICCAD David Karchmer, Jonathan Rose
1993	J	`jnl`	A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
1993	J	`jnl`	Architecture of field-programmable gate arrays. Proc. IEEE Jonathan Rose, Abbas El Gamal, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). DAC Jonathan Rose
1993	J	`jnl`	Synthesis method for field programmable gate arrays. Proc. IEEE Alberto L. Sangiovanni-Vincentelli, Abbas El Gamal, Jonathan Rose
1992	J	`jnl`	A detailed router for field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephen Brown, Jonathan Rose, Zvonko G. Vranesic
1992	C	`conf`	Improving FPGA Routing Architectures Using Architecture and CAD Interactions. ICCD Benjamin Tseng, Jonathan Rose, Stephen Brown
1992	A*	`conf`	TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections. DAC Kevin Chung, Jonathan Rose
1992	J	`jnl`	The effect of logic block architecture on FPGA performance. IEEE J. Solid State Circuits Satwant Singh, Jonathan Rose, Paul Chow, David M. Lewis
1991	A*	`conf`	Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. DAC Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
1991	J	`jnl`	Flexibility of interconnection structures for field-programmable gate arrays. IEEE J. Solid State Circuits Jonathan Rose, Stephen Brown
1991	A	`conf`	Technology Mapping on Lookup Table-Based FPGAs for Performance. ICCAD Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
1991	A*	`conf`	Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract). DAC Jonathan Rose
1990	A	`conf`	A Detailed Router for Field-Programmable Gate Arrays. ICCAD Stephen Brown, Jonathan Rose, Zvonko G. Vranesic
1990	J	`jnl`	Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency. IEEE J. Solid State Circuits Jonathan Rose, Robert J. Francis, David M. Lewis, Paul Chow
1990	A*	`conf`	Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. DAC Robert J. Francis, Jonathan Rose, Kevin Chung
1990	J	`jnl`	Parallel global routing for standard cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jonathan Rose
1990	J	`jnl`	Temperature measurement and equilibrium dynamics of simulated annealing placements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf
1988	A*	`conf`	LocusRoute: A Parallel Global Router for Standard Cells. DAC Jonathan Rose
1988	J	`jnl`	Parallel standard cell placement algorithms with quality equivalent to simulated annealing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic
1988	A	`conf`	Temperature measurement of simulated annealing placements. ICCAD Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf
1988	—	`conf`	The Parallel Decomposition and Implementation of an Integrated Circuit Global Router. PPOPP/PPEALS Jonathan Rose
1985	J	`jnl`	FERMTOR: A Tunable Multiprocessor Architecture. IEEE Micro Jonathan Rose, Wayne M. Loucks, Zvonko G. Vranesic