Jon T. Butler

108 papers B 2C 2Misc 1Journal 50Unranked 50
YearRankTypeTitle / Venue / Authors
2025 — conf
Representation of Rotation Symmetric Multiple-Valued Functions Using Decision Diagrams.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Martin Lukac
2024 J jnl
Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams.
IEICE Trans. Inf. Syst.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2023 — conf
Decomposition-Based Representation of Symmetric Multiple-Valued Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2023 J jnl
On Representation of Maximally Asymmetric Functions Based on Decision Diagrams.
FLAP
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2023 J jnl
On the distribution of sensitivities of symmetric Boolean functions.
CoRR
Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama
2022 J jnl
A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions.
J. Multiple Valued Log. Soft Comput.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2022 — conf
On Decision Diagrams for Maximally Asymmetric Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2022 — conf
On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao
2021 — conf
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2021 — conf
Linear Decompositions for Multi-Valued Input Classification Functions.
ISMVL
Tsutomu Sasao, Jon T. Butler
2020 — conf
On Optimum Linear Decomposition of Symmetric Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2020 — conf
Properties of Multiple-Valued Partition Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama
2019 — conf
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2019 — conf
Maximally Asymmetric Multiple-Valued Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao
2019 — conf
Realizing all Index Generation Functions by the Row-Shift Method.
ISMVL
Jon T. Butler, Tsutomu Sasao
2018 — conf
An Exact Method to Enumerate Decomposition Charts for Index Generation Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao
2018 — conf
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2018 J jnl
An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions.
FLAP
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2018 — ch.
Decomposition of Index Generation Functions Using a Monte Carlo Method.
Advanced Logic Synthesis
Tsutomu Sasao, Jon T. Butler
2017 J jnl
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions.
IEICE Trans. Inf. Syst.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2017 — conf
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2016 J jnl
A Parallel Approach in Computing Correlation Immunity up to Six Variables.
Int. J. Found. Comput. Sci.
Carole J. Etherington, Matthew W. Anderson, Eric Bach, Jon T. Butler, Pantelimon Stanica
2016 J jnl
A set partition number system.
Australas. J Comb.
Jon T. Butler, Tsutomu Sasao
2016 — conf
An Efficient Heuristic for Linear Decomposition of Index Generation Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2016 J jnl
Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Vincent C. Gaudet, Jon T. Butler, Robert Wille, Naofumi Homma
2015 — conf
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
2015 J jnl
High-Speed Hardware Partition Generation.
ACM Trans. Reconfigurable Technol. Syst.
Jon T. Butler, Tsutomu Sasao
2014 — conf
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
2014 — book
Applications of Zero-Suppressed Decision Diagrams
Tsutomu Sasao, Jon T. Butler
2014 J jnl
EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components.
J. Multiple Valued Log. Soft Comput.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2014 J jnl
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems.
IEICE Trans. Inf. Syst.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Mitchell A. Thornton, Theodore W. Manikas
2014 J jnl
Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators.
J. Multiple Valued Log. Soft Comput.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2013 — conf
Hardware Index to Set Partition Converter.
ARC
Jon T. Butler, Tsutomu Sasao
2013 — conf
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2012 — conf
Analysis of Multi-state Systems with Multi-state Components Using EVMDDs.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2012 — conf
Hardware Index to Permutation Converter.
IPDPS Workshops
Jon T. Butler, Tsutomu Sasao
2011 J jnl
A fast segmentation algorithm for piecewise polynomial numeric function generators.
J. Comput. Appl. Math.
Jon T. Butler, C. L. Frenzen, Njuguna Macaria, Tsutomu Sasao
2011 — conf
Fast Hardware Computation of x Mod z.
IPDPS Workshops
Jon T. Butler, Tsutomu Sasao
2011 — conf
Index to Constant Weight Codeword Converter.
ARC
Jon T. Butler, Tsutomu Sasao
2011 — conf
Numeric Function Generators Using Piecewise Arithmetic Expressions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2010 J jnl
A Quaternary Decision Diagram Machine: Optimization of Its Code.
IEICE Trans. Inf. Syst.
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
2010 J jnl
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams.
IEICE Trans. Inf. Syst.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2010 Misc conf
Enumeration of Bent Boolean Functions by Reconfigurable Computer.
FCCM
J. L. Shafer, S. W. Schneider, Jon T. Butler, Pantelimon Stanica
2010 — conf
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2010 J jnl
On the number of segments needed in a piecewise linear approximation.
J. Comput. Appl. Math.
C. L. Frenzen, Tsutomu Sasao, Jon T. Butler
2010 J jnl
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators.
Inf. Media Technol.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2010 J jnl
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators.
IPSJ Trans. Syst. LSI Des. Methodol.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2009 — conf
A Quaternary Decision Diagram Machine and the Optimization of its Code.
ISMVL
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler
2009 — conf
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions.
ISMVL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2009 — book
Progress in Applications of Boolean Functions
Tsutomu Sasao, Jon T. Butler
2008 B conf
Numerical function generators using bilinear interpolation.
FPL
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2008 C conf
Programmable Numerical Function Generators for Two-Variable Functions.
DSD
Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao
2007 C conf
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation.
DSD
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2007 J jnl
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2007 — conf
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams.
ASP-DAC
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2007 J jnl
Numerical Function Generators Using LUT Cascades.
IEEE Trans. Computers
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
2006 J jnl
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2006 — conf
Implementation of LPM Address Generators on FPGAs.
ARC
Hui Qin, Tsutomu Sasao, Jon T. Butler
2006 — conf
Implementation of Multiple-Valued CAM Functions by LUT Cascades.
ISMVL
Tsutomu Sasao, Jon T. Butler
2006 — conf
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method.
ASP-DAC
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2005 J jnl
Average Path Length of Binary Decision Diagrams.
IEEE Trans. Computers
Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura
2005 J jnl
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams.
J. Multiple Valued Log. Soft Comput.
Shinobu Nagayama, Alan Mishchenko, Tsutomu Sasao, Jon T. Butler
2005 B conf
Programmable Numerical Function Generators: Architectures and Synthesis Method.
FPL
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
2004 — conf
A fast method to derive minimum SOPs for decomposable functions.
ASP-DAC
Tsutomu Sasao, Jon T. Butler
2003 — conf
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions.
ISMVL
Jon T. Butler, Tsutomu Sasao
2002 J jnl
Bi-Partition of Shared Binary Decision Diagrams.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Munehiro Matsuura, Tsutomu Sasao, Jon T. Butler, Yukihiro Iguchi
2001 — conf
On the minimization of SOPs for bi-decomposition functions.
ASP-DAC
Tsutomu Sasao, Jon T. Butler
2001 J jnl
On the number of generators for transeunt triangles.
Discret. Appl. Math.
Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko
2001 J jnl
Worst and Best Irredundant Sum-of-Products Expressions.
IEEE Trans. Computers
Tsutomu Sasao, Jon T. Butler
2000 J jnl
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich
2000 — conf
Experiments on FPRM Expressions for Partially Symmetric Logic Functions.
ISMVL
Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko
1998 — conf
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels.
ISMVL
Jon T. Butler, Tsutomu Sasao
1997 J jnl
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions.
IEEE Trans. Computers
Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III
1997 — conf
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions.
ISMVL
Tsutomu Sasao, Jon T. Butler
1997 J jnl
Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits.
IEEE Trans. Computers
Kriss A. Schueller, Jon T. Butler
1996 — conf
A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams.
ISMVL
Tsutomu Sasao, Jon T. Butler
1996 — conf
Planarity in ROMDD's of Multiple-Valued Symmetric Functions.
ISMVL
Jon T. Butler, J. L. Nowlin, Tsutomu Sasao
1995 — conf
Planar Multiple-Valued Decision Diagrams.
ISMVL
Tsutomu Sasao, Jon T. Butler
1994 — conf
A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion.
ISMVL
Tsutomu Sasao, Jon T. Butler
1994 — conf
Multiple-Valued Combinational Circuits with Feedback.
ISMVL
Jon T. Butler, Tsutomu Sasao
1994 — conf
Multiple-Valued Logic Operations with Universal Literals.
ISMVL
Gerhard W. Dueck, Jon T. Butler
1993 — conf
Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing.
ISMVL
Cem Yildirim, Jon T. Butler, Chyan Yang
1992 — conf
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing.
ISMVL
Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler
1992 J jnl
On the Design of Cost-Tables for Realizing Multiple-Valued Circuits.
IEEE Trans. Computers
Kriss A. Schueller, Jon T. Butler
1992 — conf
Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991.
ISMVL
Susan W. Butler, Jon T. Butler
1991 J jnl
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.
IEEE Trans. Computers
Parthasarathy P. Tirumalai, Jon T. Butler
1991 — conf
The Design of Current Mode CMOS Multiple-Valued Circuits.
ISMVL
Young-Hoon Chang, Jon T. Butler
1991 — conf
Worst Case Number of Terms in Symmetric Multiple-Valued Functions.
ISMVL
Jon T. Butler, Kriss A. Schueller
1990 J jnl
A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs.
IEEE Trans. Computers
Joo-Kang Lee, Jon T. Butler
1990 — conf
A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach.
ISMVL
Jon T. Butler, Hans G. Kerkhoff, Siep Onneweer
1990 — conf
HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays.
ISMVL
John M. Yurchak, Jon T. Butler
1990 J jnl
On the Equivalence of Cost Functions in the Design of Circuits by Costtable.
IEEE Trans. Computers
Jon T. Butler, Kriss A. Schueller
1989 J jnl
On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions.
IEEE Trans. Computers
Edward A. Bender, Jon T. Butler
1988 J jnl
Multiple-Valued CCD Circuits.
Computer
Jon T. Butler, Hans G. Kerkhoff
1988 J jnl
Multiple-Valued Logic - Guest Editor's Introduction.
Computer
Jon T. Butler
1985 J jnl
Enumeration of Structured Flowcharts
J. ACM
Edward A. Bender, Jon T. Butler
1982 J jnl
On the relationship between propagating context-dependent lindenmayer systems and cellular automata systems.
Inf. Sci.
Jon T. Butler
1981 J jnl
Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms.
IEEE Trans. Computers
Jon T. Butler
1980 J jnl
Synthesis of One-Dimensional Binary Scope-2 Flexible Cellular Systems from Initial Final Configuration Pairs
Inf. Control.
Patrick E. White, Jon T. Butler
1979 J jnl
Decomposable Maps in General Tessellation Structures.
J. Comput. Syst. Sci.
Jon T. Butler
1979 J jnl
Synthesis of One-Dimensional Binary Cellular Automata Systems from Composite Local Maps
Inf. Control.
Jon T. Butler
1978 J jnl
Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates.
J. ACM
Jon T. Butler
1978 J jnl
Asymptotic Aproximations for the Number of Fanout-Free Functions.
IEEE Trans. Computers
Edward A. Bender, Jon T. Butler
1978 J jnl
Tandem Networks of Universal Cells.
IEEE Trans. Computers
Jon T. Butler
1976 J jnl
Restricted Cellular Networks.
IEEE Trans. Computers
Jon T. Butler
1975 J jnl
On the Number of Functions Realized by Cascades and Disjunctive Networks.
IEEE Trans. Computers
Jon T. Butler
1974 J jnl
A Note on Cellular Automata Simulations
Inf. Control.
Jon T. Butler
1973 J jnl
Some Characteristics of Universal Cell Nets.
IEEE Trans. Computers
Jon T. Butler, Kenneth J. Breeding