John Wawrzynek

135 papers A* 8A 22B 13C 2Misc 13Journal 43Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	Chip Placement with Diffusion Models. ICML Vint Lee, Minh Nguyen, Leena Elzeiny, Chun Deng, Pieter Abbeel, John Wawrzynek
2025	—	`conf`	DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits. ASP-DAC Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek
2025	J	`jnl`	DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits. CoRR Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek
2025	—	`conf`	High-Effort Logic Synthesis Using Randomized Transduction. ASP-DAC Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Dino Ruic, Xiaoqing Xu
2025	A	`conf`	High-Throughput SAT Sampling. DATE Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, John Wawrzynek
2025	J	`jnl`	High-Throughput SAT Sampling. CoRR Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, John Wawrzynek
2025	A	`conf`	Lessons from 40 Years of Reconfigurable Computing. FPGA John Wawrzynek
2025	—	`conf`	ML-Inspired Logic Synthesis: Improving Multiplier Circuits. MLCAD Yukio Miyasaka, Walter Lau Neto, Eleonora Testa, Anika Prasad, Michael Shuster, Reto Zimmermann, Patrick Vuillod, Alan Mishchenko, John Wawrzynek, Luca G. Amarù
2025	—	`conf`	Recurrent CircuitSAT Sampling for Sequential Circuits. MLCAD Arash Ardakani, Kevin He, John Wawrzynek
2025	J	`jnl`	Recurrent CircuitSAT Sampling for Sequential Circuits. CoRR Arash Ardakani, Kevin He, John Wawrzynek
2024	J	`jnl`	Chip Placement with Diffusion. CoRR Vint Lee, Chun Deng, Leena Elzeiny, Pieter Abbeel, John Wawrzynek
2024	A*	`conf`	Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas. DAC Arash Ardakani, Minwoo Kang, Kevin He, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek
2024	Misc	`conf`	Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN. FCCM Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Nicholas J. Fraser
2023	A	`conf`	Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. DATE Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek
2023	B	`conf`	SPADES: A Productive Design Flow for Versal Programmable Logic. FPL Tan Nguyen, Zachary Blair, Stephen Neuendorffer, John Wawrzynek
2022	B	`conf`	Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design. ISPASS Qijing Huang, Charles Hong, John Wawrzynek, Mahesh Subedar, Yakun Sophia Shao
2021	A	`conf`	CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs. FPGA Qijing Huang, Dequan Wang, Zhen Dong, Yizhao Gao, Yaohui Cai, Tian Li, Bichen Wu, Kurt Keutzer, John Wawrzynek
2021	A*	`conf`	CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. ISCA Qijing Huang, Aravind Kalaiah, Minwoo Kang, James Demmel, Grace Dinh, John Wawrzynek, Thomas Norell, Yakun Sophia Shao
2021	J	`jnl`	CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. CoRR Qijing Huang, Minwoo Kang, Grace Dinh, Thomas Norell, Aravind Kalaiah, James Demmel, John Wawrzynek, Yakun Sophia Shao
2021	Misc	`conf`	HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. FCCM Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer
2021	J	`jnl`	HAO: Hardware-aware neural Architecture Optimization for Efficient Inference. CoRR Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer
2020	J	`jnl`	Algorithm-hardware Co-design for Deformable Convolution. CoRR Qijing Huang, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek
2020	—	`conf`	AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. MLSys Ameer Haj-Ali, Qijing (Jenny) Huang, William S. Moses, John Xiang, Krste Asanovic, John Wawrzynek, Ion Stoica
2020	J	`jnl`	AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. CoRR Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek
2020	J	`jnl`	CoDeNet: Algorithm-hardware Co-design for Deformable Convolution. CoRR Zhen Dong, Dequan Wang, Qijing Huang, Yizhao Gao, Yaohui Cai, Bichen Wu, Kurt Keutzer, John Wawrzynek
2020	J	`jnl`	ProTuner: Tuning Programs with Monte Carlo Tree Search. CoRR Ameer Haj-Ali, Hasan Genc, Qijing Huang, William S. Moses, John Wawrzynek, Krste Asanovic, Ion Stoica
2020	—	`conf`	SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek
2019	—	`conf`	Algorithm-hardware Co-design for Deformable Convolution. EMC2@NeurIPS Qijing Huang, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek
2019	B	`conf`	Antenna Array Geometries for Directional Wireless Networks. WCNC James C. Martin, Robert W. Brodersen, John Wawrzynek
2019	Misc	`conf`	AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning. FCCM Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek
2019	J	`jnl`	AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning. CoRR Ameer Haj Ali, Qijing Huang, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek
2019	A	`conf`	Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration. ICCAD Qijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma, Guohao Dai, Robert Quitt, Krste Asanovic, John Wawrzynek
2019	—	`conf`	GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs. ASP-DAC Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek
2019	J	`jnl`	HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing. IEEE Trans. Computers Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek
2019	A	`conf`	Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
2018	A*	`conf`	AWStream: adaptive wide-area streaming analytics. SIGCOMM Ben Zhang, Xin Jin, Sylvia Ratnasamy, John Wawrzynek, Edward A. Lee
2018	Misc	`conf`	NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads. FCCM Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek
2018	B	`conf`	Receiver Adaptive Beamforming and Interference of Indoor Environments in mmWave. PIMRC James C. Martin, Robert W. Brodersen, John Wawrzynek
2018	J	`jnl`	Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. CoRR Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer
2017	—	`conf`	Compressive sensing and sparse antenna arrays for indoor 3-D microwave imaging. EUSIPCO Simon Scott, John Wawrzynek
2017	A	`conf`	OLAF'17: Third International Workshop on Overlay Architectures for FPGAs. FPGA Hayden Kwok-Hay So, John Wawrzynek
2017	J	`jnl`	Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017). CoRR Hayden Kwok-Hay So, John Wawrzynek
2017	C	`conf`	SLSR: A flexible middleware localization service architecture. IPIN Filip Lemic, Vlado Handziski, Ivan Azcarate, John Wawrzynek, Jan M. Rabaey, Adam Wolisz
2017	B	`conf`	Selection and Aggregation of Location Information Provisioning Services. ICCCN Filip Lemic, Vlado Handziski, Mladen Miksa, Jan M. Rabaey, John Wawrzynek, Adam Wolisz
2017	—	`conf`	Synthesis of program binaries into FPGA accelerators with runtime dependence validation. FPT Shaoyi Cheng, Qijing Huang, John Wawrzynek
2016	J	`jnl`	High Level Synthesis with a Dataflow Architectural Template. CoRR Shaoyi Cheng, John Wawrzynek
2016	B	`conf`	Localization as a feature of mmWave communication. IWCMC Filip Lemic, James C. Martin, Christopher Yarp, Douglas S. Chan, Vlado Handziski, Robert W. Brodersen, Gerhard P. Fettweis, Adam Wolisz, John Wawrzynek
2016	A	`conf`	OLAF'16: Second International Workshop on Overlay Architectures for FPGAs. FPGA Hayden Kwok-Hay So, John Wawrzynek
2016	J	`jnl`	Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016). CoRR Hayden Kwok-Hay So, John Wawrzynek
2016	A	`conf`	Synthesis of statically analyzable accelerator networks from sequential programs. ICCAD Shaoyi Cheng, John Wawrzynek
2016	J	`jnl`	Toward a Global Data Infrastructure. IEEE Internet Comput. Nitesh Mor, Ben Zhang, John Kolb, Douglas S. Chan, Nikhil Goyal, Nicholas Sun, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz
2016	C	`conf`	Toward standardized localization service. IPIN Filip Lemic, Vlado Handziski, Nitesh Mor, Jan M. Rabaey, John Wawrzynek, Adam Wolisz
2015	J	`jnl`	ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism. Microprocess. Microsystems Mingjie Lin, Shaoyi Cheng, Ronald F. DeMara, John Wawrzynek
2015	—	`conf`	The Cloud is Not Enough: Saving IoT from the Cloud. HotCloud Ben Zhang, Nitesh Mor, John Kolb, Douglas S. Chan, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz
2015	—	`conf`	The Cloud is Not Enough: Saving IoT from the Cloud. HotStorage Ben Zhang, Nitesh Mor, John Kolb, Douglas S. Chan, Ken Lutz, Eric Allman, John Wawrzynek, Edward A. Lee, John Kubiatowicz
2014	—	`conf`	Architectural synthesis of computational pipelines with decoupled memory access. FPT Shaoyi Cheng, John Wawrzynek
2014	J	`jnl`	The Swarm at the Edge of the Cloud. IEEE Des. Test Edward A. Lee, Björn Hartmann, John Kubiatowicz, Tajana Simunic Rosing, John Wawrzynek, David Wessel, Jan M. Rabaey, Kris Pister, Alberto L. Sangiovanni-Vincentelli, Sanjit A. Seshia, David T. Blaauw, Prabal Dutta, Kevin Fu, Carlos Guestrin, Ben Taskar, Roozbeh Jafari, Douglas L. Jones, Vijay Kumar, Rahul Mangharam, George J. Pappas, Richard M. Murray, Anthony Rowe
2013	—	`conf`	Extracting memory-level parallelism through reconfigurable hardware traces. ReConFig Mingjie Lin, Shaoyi Cheng, John Wawrzynek
2013	Misc	`conf`	Reconfigurable computing in the era of post-silicon scaling [panel discussion]. FCCM Eric S. Chung, Doug Burger, Mike Butts, Jan Gray, Chuck Thacker, Kees A. Vissers, John Wawrzynek
2012	A*	`conf`	Chisel: constructing hardware in a Scala embedded language. DAC Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic
2012	Misc	`conf`	Exploiting Memory-Level Parallelism in Reconfigurable Accelerators. FCCM Shaoyi Cheng, Mingjie Lin, Hao Jun Liu, Simon Scott, John Wawrzynek
2012	J	`jnl`	Exploring Many-Core Design Templates for FPGAs and ASICs. Int. J. Reconfigurable Comput. Ilia A. Lebedev, Christopher W. Fletcher, Shaoyi Cheng, James C. Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek
2012	J	`jnl`	Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience. J. Electr. Comput. Eng. Mingjie Lin, Yu Bai, John Wawrzynek
2011	—	`conf`	Advances and challenges of computing with FPGAs. CICC John Wawrzynek
2011	A	`conf`	Bridging the GPGPU-FPGA efficiency gap. FPGA Christopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek
2011	—	`conf`	Discriminatively Fortified Computing with Reconfigurable Digital Fabric. HASE Mingjie Lin, Yu Bai, John Wawrzynek
2011	A	`ed.`	Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011 FPGA John Wawrzynek, Katherine Compton
2011	J	`jnl`	RTP Payload Format for MIDI. RFC John Lazzaro, John Wawrzynek
2011	A	`conf`	Should the academic community launch an open-source FPGA device and tools effort?: evening panel. FPGA John Wawrzynek
2011	A	`conf`	Using many-core architectural templates for FPGA-based computing (abstract only). FPGA Mingjie Lin, Shaoyi Cheng, John Wawrzynek
2010	—	`conf`	Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations. ReConFig Mingjie Lin, Shaoyi Cheng, John Wawrzynek
2010	J	`jnl`	Exploring FPGA Routing Architecture Stochastically. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mingjie Lin, John Wawrzynek, Abbas El Gamal
2010	A	`conf`	High-throughput bayesian computing machine with reconfigurable hardware. FPGA Mingjie Lin, Ilia A. Lebedev, John Wawrzynek
2010	J	`jnl`	Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mingjie Lin, John Wawrzynek
2010	—	`conf`	MARC: A Many-Core Approach to Reconfigurable Computing. ReConFig Ilia A. Lebedev, Shaoyi Cheng, Austin Doupnik, James C. Martin, Christopher W. Fletcher, Daniel Burke, Mingjie Lin, John Wawrzynek
2010	B	`conf`	OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices. FPL Mingjie Lin, Ilia A. Lebedev, John Wawrzynek
2010	A	`ed.`	Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010 FPGA Peter Y. K. Cheung, John Wawrzynek
2009	A	`conf`	A design methodology for domain-optimized power-efficient supercomputing. SC Marghoob Mohiyuddin, Mark Murphy, Leonid Oliker, John Shalf, John Wawrzynek, Samuel Williams
2009	J	`jnl`	A view of the parallel computing landscape. Commun. ACM Krste Asanovic, Rastislav Bodík, James Demmel, Tony M. Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel, Katherine A. Yelick
2009	—	`conf`	Using adaptive routing to compensate for performance heterogeneity. NOCS Yury Markovsky, Yatish Patel, John Wawrzynek
2008	J	`jnl`	Workloads of the Future. IEEE Des. Test Comput. Jan M. Rabaey, Daniel Burke, Ken Lutz, John Wawrzynek
2007	B	`conf`	Adventures with a Reconfigurable Research Platform. FPL John Wawrzynek
2007	B	`conf`	RAMP Blue: A Message-Passing Manycore System in FPGAs. FPL Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz
2007	J	`jnl`	RAMP: Research Accelerator for Multiple Processors. IEEE Micro John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
2006	J	`jnl`	An Implementation Guide for RTP MIDI. RFC John Lazzaro, John Wawrzynek
2006	J	`jnl`	RTP Payload Format for MIDI. RFC John Lazzaro, John Wawrzynek
2006	—	`conf`	Research accelerator for multiple processors. Hot Chips Symposium David A. Patterson, Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan M. Rabaey, John Wawrzynek
2006	J	`jnl`	Stochastic spatial routing for reconfigurable networks. Microprocess. Microsystems André DeHon, Randy Huang, John Wawrzynek
2006	J	`jnl`	Stream computations organized for reconfigurable execution. Microprocess. Microsystems André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek
2005	J	`jnl`	BEE2: A High-End Reconfigurable Computing System. IEEE Des. Test Comput. Chen Chang, John Wawrzynek, Robert W. Brodersen
2005	B	`conf`	Defect Tolerance in Multiple-FPGA Systems. FPL Zohair Hyder, John Wawrzynek
2005	—	`conf`	The Design And Application Of A High-End Reconfigurable Computing System. ERSA Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen
2004	A	`conf`	The SFRA: a corner-turn FPGA architecture. FPGA Nicholas Weaver, John R. Hauser, John Wawrzynek
2003	J	`jnl`	Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics. IEEE Micro John Wawrzynek, Keith Diefendorff
2003	A	`conf`	Post-placement C-slow retiming for the xilinx virtex FPGA. FPGA Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek
2003	—	`conf`	Quality based compute-resource allocation in real-time signal processing. ICASSP (2) Joseph Yeh, John Wawrzynek
2003	A	`conf`	Stochastic, spatial routing for hypergraphs, trees, and meshes. FPGA Randy Huang, John Wawrzynek, André DeHon
2002	A	`conf`	Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. FPGA Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon
2002	Misc	`conf`	Hardware-Assisted Fast Routing. FCCM André DeHon, Randy Huang, John Wawrzynek
2002	Misc	`conf`	The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks. FCCM Nicholas Weaver, John Wawrzynek
2001	B	`conf`	A case for network musical performance. NOSSDAV John Lazzaro, John Wawrzynek
2000	—	`conf`	A Comparison of the AES Candidates Amenability to FPGA Implementation. AES Candidate Conference Nicholas Weaver, John Wawrzynek
2000	Misc	`conf`	Adapting software pipelining for reconfigurable computing. CASES Timothy J. Callahan, John Wawrzynek
2000	B	`conf`	Stream Computations Organized for Reconfigurable Execution (SCORE). FPL Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon
2000	J	`jnl`	The Garp Architecture and C Compiler. Computer Timothy J. Callahan, John R. Hauser, John Wawrzynek
1999	Misc	`conf`	A fixed-point recursive digital oscillator for additive synthesis of audio. ICASSP Todd D. Hodes, John R. Hauser, John Wawrzynek, Adrian Freed, David Wessel
1999	A	`conf`	HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. FPGA William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon
1999	J	`jnl`	JPEG Quality Transcoding Using Neural Networks Trained With a Perceptual Error Measure. Neural Comput. John Lazzaro, John Wawrzynek
1999	J	`jnl`	Real products, real technology Guest Editor's Introduction]. IEEE Micro Norman P. Jouppi, John Wawrzynek
1999	A*	`conf`	Reconfigurable Computing: What, Why, and Implications for Design Automation. DAC André DeHon, John Wawrzynek
1998	A	`conf`	Fast Module Mapping and Placement for Datapaths in FPGAs. FPGA Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek
1998	B	`conf`	Instruction-Level Parallelism for Reconfigurable Computing. FPL Timothy J. Callahan, John Wawrzynek
1998	Misc	`conf`	Object Oriented Circuit-Generators in Java. FCCM Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek
1997	J	`jnl`	A micropower analog circuit implementation of hidden Markov model state decoding. IEEE J. Solid State Circuits John Lazzaro, John Wawrzynek, Richard P. Lippmann
1997	Misc	`conf`	Datapath-oriented FPGA mapping and placement for configurable computing. FCCM Timothy J. Callahan, John Wawrzynek
1997	Misc	`conf`	Garp: a MIPS processor with a reconfigurable coprocessor. FCCM John R. Hauser, John Wawrzynek
1996	—	`conf`	A Micropower Analog VLSI HMM State Decoder for Wordspotting. NIPS John Lazzaro, John Wawrzynek, Richard Lippmann
1996	J	`jnl`	Spert-II: A Vector Microprocessor System. Computer John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, Nelson Morgan
1995	—	`conf`	A multi-sender asynchronous extension to the AER protocol. ARVLSI John Lazzaro, John Wawrzynek
1995	—	`conf`	SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training. NIPS John Wawrzynek, Krste Asanovic, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan
1995	—	`conf`	Silicon Models for Auditory Scene Analysis. NIPS John Lazzaro, John Wawrzynek
1994	J	`jnl`	Systems technologies for silicon auditory models. IEEE Micro John Lazzaro, John Wawrzynek, Alan Kramer
1993	J	`jnl`	Designing A Connectionist Network Supercomputer. Int. J. Neural Syst. Krste Asanovic, James Beck, Jerry Feldman, Nelson Morgan, John Wawrzynek
1993	J	`jnl`	Silicon auditory processors as computer peripherals. IEEE Trans. Neural Networks John Lazzaro, John Wawrzynek, Misha Mahowald, Massimo Sivilotti, Dave Gillespie
1993	J	`jnl`	The design of a neuro-microprocessor. IEEE Trans. Neural Networks John Wawrzynek, Krste Asanovic, Nelson Morgan
1993	J	`jnl`	Using simulations of reduced precision arithmetic to design a neuro-microprocessor. J. VLSI Signal Process. Krste Asanovic, Nelson Morgan, John Wawrzynek
1992	—	`conf`	SPERT: a VLIW/SIMD microprocessor for artificial neural network computations. ASAP Krste Asanovic, James Beck, Brian Kingsbury, Phil Kohn, Nelson Morgan, John Wawrzynek
1992	—	`conf`	Silicon Auditory Processors as Computer Peripherals. NIPS John Lazzaro, John Wawrzynek, Misha Mahowald, Massimo Sivilotti, Dave Gillespie
1991	A*	`conf`	A Two-Dimensional Topological Compactor With Octagonal Geometry. DAC Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya
1991	A*	`conf`	Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine. ASPLOS David E. Culler, Anurag Sah, Klaus E. Schauser, Thorsten von Eicken, John Wawrzynek
1990	—	`conf`	A Multimedia Digital Signal Processing Tutoring System. ICMC Sam Pointer, John Wawrzynek, David Wessel
1990	—	`conf`	VLSI Parallel Processing for Musical Sound Synthesis. ICMC John Wawrzynek, Thorsten von Eicken
1989	—	`conf`	The Center for New Music and Audio Technologies. ICMC David Wessel, Richard Felciano, Adrian Freed, John Wawrzynek
1987	—	`—`	VLSI Concurrent Computation for Music Synthesis. John Wawrzynek
1984	—	`conf`	A VLSI Approach to Sound Synthesis. ICMC John Wawrzynek, Carver Mead, Tzu-Mu Lin, Hsui-Lin Liu, Lounette M. Dyer