John V. McCanny

109 papers A 2B 4C 5Misc 22Journal 28Unranked 48
YearRankTypeTitle / Venue / Authors
2017 — conf
New sensing technique for detecting application layer DDoS attacks targeting back-end database resources.
ICC
David Beckett, Sakir Sezer, John V. McCanny
2012 — conf
Design of interlock-free combined allocators for Networks-on-Chip.
SoCC
Ye Lu, Changlin Chen, John V. McCanny, Sakir Sezer
2011 — conf
Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip.
SoCC
Ye Lu, John V. McCanny, Sakir Sezer
2011 B conf
Generic Low-Latency NoC Router Architecture for FPGA Computing Systems.
FPL
Ye Lu, John V. McCanny, Sakir Sezer
2011 J jnl
QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers.
IEEE Trans. Signal Process.
Lei Ma, Kevin Dickson, John McAllister, John V. McCanny
2011 — conf
The Impact of Global Routing on the Performance of NoCs in FPGAs.
ReConFig
Ye Lu, John V. McCanny, Sakir Sezer
2010 B conf
Advanced Multithreading Architecture with Hardware Based Scheduling.
FPL
Ye Lu, Sakir Sezer, John V. McCanny
2010 — conf
Design and analysis of an advanced static blocked multithreading architecture.
SoCC
Ye Lu, Sakir Sezer, John V. McCanny
2010 J jnl
Evaluation of Random Delay Insertion against DPA on FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Yingxi Lu, Máire O'Neill, John V. McCanny
2010 — conf
High-Performance random data lookup for network processing.
SoCC
Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns
2010 J jnl
Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding.
IET Comput. Digit. Tech.
Liang Lu, John V. McCanny, Sakir Sezer
2010 C conf
TLM2.0 based timing accurate modeling method for complex NoC systems.
ISCAS
Ye Lu, Sakir Sezer, John V. McCanny
2009 — conf
DDR3 based lookup circuit for high-performance network processing.
SoCC
Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns
2009 — conf
Is the differential frequency-based attack effective against random delay insertion?
SiPS
Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh
2009 — conf
NFA decomposition and multiprocessing architecture for parallel regular expression processing.
SoCC
Yongping Liu, Sakir Sezer, John V. McCanny
2009 J jnl
Subpixel Interpolation Architecture for Multistandard Video Motion Estimation.
IEEE Trans. Circuits Syst. Video Technol.
Liang Lu, John V. McCanny, Sakir Sezer
2008 C conf
Differential Power Analysis of a SHACAL-2 hardware implementation.
ISCAS
Yingxi Lu, Máire O'Neill, John V. McCanny
2008 — conf
FPGA implementation and analysis of random delay insertion countermeasure against DPA.
FPT
Yingxi Lu, Máire O'Neill, John V. McCanny
2008 J jnl
From Bit Level Systolic Arrays to HDTV Processor Chips.
J. Signal Process. Syst.
Roger F. Woods, John V. McCanny, John G. McWhirter
2008 J jnl
Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication.
J. Signal Process. Syst.
Yen-Kuang Chen, David W. Lin, John V. McCanny, Edwin Hsing-Mean Sha
2008 — conf
High performance IP lookup circuit using DDR SDRAM.
SoCC
Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.
2008 Misc conf
Modified givens rotations and their application to matrix inversion.
ICASSP
Lei Ma, Kevin Dickson, John McAllister, John V. McCanny
2008 — conf
Multi-standard sub-pixel interpolation architecture for video Motion Estimation.
SoCC
Liang Lu, John V. McCanny, Sakir Sezer
2008 — conf
Reduced-complexity MSGR-based matrix inversion.
SiPS
Lei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai
2007 — conf
A versatile content addressable memory architecture.
SoCC
Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns
2007 — conf
Exploring technology related design-space limitations of high performance network processing.
ESSCIRC
John V. McCanny, Sakir Sezer, Máire O'Neill
2007 — conf
From Special Purpose VLSI Architectures to HDTV Processors and Gigabit Wireless Systems.
DSP
John V. McCanny
2007 — conf
Novel Content Addressable Memory Architecture for Adaptive Systems.
AHS
Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns
2007 — conf
Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression.
ASAP
Liang Lu, John V. McCanny, Sakir Sezer
2007 — conf
Reconfigurable video motion estimation processor.
SoCC
Liang Lu, John V. McCanny, Sakir Sezer
2007 — conf
Systolic Array Based Architecture for Variable Block-Size Motion Estimation.
AHS
Liang Lu, John V. McCanny, Sakir Sezer
2006 — conf
An Adaptable And Scalable Asymmetric Cryptographic Processor.
ASAP
Neil Smyth, Máire McLoone, John V. McCanny
2006 — conf
Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup.
AICT/ICIW
Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny
2006 A conf
Design and analysis of matching circuit architectures for a closest match lookup.
IPDPS
Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny
2006 — conf
From Bit Level Systolic Arrays to HDTV Processor Chips.
ASAP
John V. McCanny, Roger F. Woods, John G. McWhirter
2006 J jnl
Hardware Elliptic Curve Cryptographic Processor Over $\rm GF(p)$.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ciaran McIvor, Máire McLoone, John V. McCanny
2006 J jnl
WLAN security processor.
IEEE Trans. Circuits Syst. I Regul. Pap.
Neil Smyth, Máire McLoone, John V. McCanny
2005 J jnl
Application-specific instruction set processor for SoC implementation of modern signal processing algorithms.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhaohui Liu, Kevin Dickson, John V. McCanny
2005 — conf
Hardware Design of Sphere Decoding for MIMO Systems.
SoCC
Zhaohui Liu, Kevin Dickson, John V. McCanny
2005 — conf
High-Radix Systolic Modular Multiplication on Reconfigurable Hardware.
FPT
Ciaran McIvor, Máire McLoone, John V. McCanny
2004 J jnl
A VLSI architecture for variable block size video motion estimation.
IEEE Trans. Circuits Syst. II Express Briefs
Swee Yeow Yap, John V. McCanny
2004 — conf
Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication.
FPT
Máire McLoone, Ciaran McIvor, John V. McCanny
2004 Misc conf
FPGA Montgomery Multiplier Architectures - A Comparison.
FCCM
Ciaran McIvor, Máire McLoone, John V. McCanny
2004 — conf
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p).
ISCAS (3)
Ciaran McIvor, Máire McLoone, John V. McCanny
2004 J jnl
Reusable silicon IP cores for discrete wavelet transform applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shahid Masud, John V. McCanny
2003 — conf
A VLSI Architecture for Advanced Video Coding Motion Estimation.
ASAP
Swee Yeow Yap, John V. McCanny
2003 — conf
A floating-point CORDIC based SVD processor.
ASAP
Zhaohui Liu, Kevin Dickson, John V. McCanny
2003 — conf
A high-speed, low latency RSA decryption silicon core.
ISCAS (4)
Ciaran McIvor, Máire McLoone, John V. McCanny
2003 J jnl
Generic SoC QR array processor for adaptive beamforming.
IEEE Trans. Circuits Syst. II Express Briefs
Zhaohui Liu, John V. McCanny, Gaye Lightbody, Richard L. Walke
2003 — conf
Implementation of adaptive beamforming based on QR decomposition for CDMA.
ICASSP (2)
Zhaohui Liu, John V. McCanny
2003 J jnl
Rijndael FPGA Implementations Utilising Look-Up Tables.
J. VLSI Signal Process.
Máire McLoone, John V. McCanny
2003 B conf
Very High Speed 17 Gbps SHACAL Encryption Architecture.
FPL
Máire McLoone, John V. McCanny
2002 Misc conf
A hybrid mixed cost-function TEQ initialization algorithm for ADSL modems.
ICASSP
Kok Sing Yap, John V. McCanny
2002 — conf
A mixed cost-function adaptive algorithm for ADSL time-domain equalization.
ICC
Kok Sing Yap, John V. McCanny
2002 Misc conf
Design and implementation of the symmetrically extended 2-D Wavelet Transform.
ICASSP
Paul V. McCanny, Shahid Masud, John V. McCanny
2002 — conf
Efficient single-chip implementation of SHA-384 and SHA-512.
FPT
Máire McLoone, John V. McCanny
2002 — conf
VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform.
EUSIPCO
Paul V. McCanny, John V. McCanny, Shahid Masud
2001 — conf
An efficient architecture for the 2-D biorthogonal discrete wavelet transform.
ICIP (3)
Paul V. McCanny, Shahid Masud, John V. McCanny
2001 J jnl
Design of Silicon IP Cores for Biorthogonal Wavelet Transforms.
J. VLSI Signal Process.
Shahid Masud, John V. McCanny
2001 Misc conf
Generic scheduling methods for a linear QR array SoC processor.
ICASSP
Zhaohui Liu, Gaye Lightbody, Richard L. Walke, Yi Hu, John V. McCanny
2001 A conf
High Performance Single-Chip FPGA Rijndael Algorithm Implementations.
CHES
Máire McLoone, John V. McCanny
2001 B conf
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm.
FPL
Máire McLoone, John V. McCanny
2000 J jnl
Linear QR Architecture for a Single Chip Adaptive Beamformer.
J. VLSI Signal Process.
Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny
2000 J jnl
Online CORDIC algorithm and VLSI architecture for implementing QR-array processors.
IEEE Trans. Signal Process.
Robert Hamill, John V. McCanny, Richard L. Walke
2000 Misc conf
Wavelet packet transforms for system-on-chip applications.
ICASSP
Shahid Masud, John V. McCanny
1999 Misc conf
Novel mapping of a linear QR architecture.
ICASSP
Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny
1999 J jnl
Rapid design of application specific FFT cores.
IEEE Trans. Signal Process.
Tiong Jiu Ding, John V. McCanny, Yunsheng Hu
1999 Misc conf
Rapid design of discrete orthonormal wavelet transforms using silicon IP components.
ICASSP
Shahid Masud, John V. McCanny
1998 Misc conf
Discrete cosine transform generator for VLSI synthesis.
ICASSP
Jill K. Hunter, John V. McCanny
1998 C conf
Rapid Design of Discrete Orthonormal Wavelet Transforms.
International Workshop on Rapid System Prototyping
Shahid Masud, John V. McCanny
1998 — conf
Rapid design of discrete transform cores.
EUSIPCO
Jill K. Hunter, John V. McCanny
1997 J jnl
Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS".
J. VLSI Signal Process.
David W. Trainor, Roger F. Woods, John V. McCanny
1997 Misc conf
Hierarchical VHDL libraries for DSP ASIC design.
ICASSP
John V. McCanny, Douglas Ridge, Yi Hu, Jill K. Hunter
1996 J jnl
A 64-point Fourier transform chip for video motion compensation using phase correlation.
IEEE J. Solid State Circuits
Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
1996 — conf
A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation.
ASAP
Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
1996 — conf
Error analysis of FFT architectures for digital video applications.
ICECS
Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
1996 — conf
Synthesisable high performance adaptive equaliser and Viterbi decoder for the Class-IV PRML channel.
ICECS
B. D. E. Smith, John V. McCanny
1995 J jnl
A Systematic Methodology for the Design of High Performance Recursive Digital Filters.
IEEE Trans. Computers
Stephen E. McQuillan, John V. McCanny
1995 J jnl
VLSI architectures for vector quantization.
J. VLSI Signal Process.
M. Yan, John V. McCanny, Yi Hu
1994 — conf
Automated design of DSP array processor chips.
ASAP
John V. McCanny, Yi Hu, M. Yan
1994 J jnl
Fast VLSI algorithms for division and square root.
J. VLSI Signal Process.
Stephen E. McQuillan, John V. McCanny
1993 C conf
New algorithms and VLSI architectures for SRT division and square root.
IEEE Symposium on Computer Arithmetic
Stephen E. McQuillan, John V. McCanny, Robert Hamill
1992 — conf
Algorithms and architectures for high performance recursive filtering.
ASAP
Stephen E. McQuillan, John V. McCanny
1992 J jnl
High performance VLSI architecture for Wave Digital Filtering.
J. VLSI Signal Process.
Rajinder Jit Singh, John V. McCanny
1992 J jnl
Systolic inner product arrays with automatic word rounding.
J. VLSI Signal Process.
M. Yan, John V. McCanny
1992 Misc conf
The systematic design of high performance digital filters.
ICASSP
B. P. McGovern, Roger F. Woods, John V. McCanny
1991 — conf
A 40 megasample IIR filter chip.
ASAP
O. C. McNally, John V. McCanny, Roger F. Woods
1991 Misc conf
A VLSI architecture for multiplication, division and square root.
ICASSP
Stephen E. McQuillan, John V. McCanny
1991 — conf
A wave digital filter three-port adaptor with fine grained pipelining.
ASAP
Rajinder Jit Singh, John V. McCanny
1991 Misc conf
Design and test of a bit parallel 2nd order IIR filter structure.
ICASSP
O. C. McNally, William P. Marnane, John V. McCanny
1991 — conf
Design of a Highly Pipelined 2nd Order IIR Filter Chip.
VLSI
O. C. McNally, John V. McCanny, Roger F. Woods
1991 — conf
On the use of most significant digit first arithmetic in the design of high performance DSP chips.
Algorithms and Parallel VLSI Architectures
John V. McCanny
1990 J jnl
A bit-level systolic architecture for implementing a VQ tree search.
J. VLSI Signal Process.
M. Yan, John V. McCanny
1990 C conf
Optimized bit level architectures for IIR filtering.
ICCD
O. C. McNally, John V. McCanny, Roger F. Woods
1990 Misc conf
Pipelined two-port adaptor for wave digital filtering.
ICASSP
Rajinder Jit Singh, John V. McCanny, Roger F. Woods
1990 — conf
Systolic VLSI compiler (SVC) for high performance vector quantisation chips.
ASAP
Y. Hu, John V. McCanny, M. Yan
1990 — conf
Systolic two-port adaptor for high performance wave digital filtering.
ASAP
Rajinder Jit Singh, John V. McCanny
1990 J jnl
The use of data dependence graphs in the design of bit-level systolic arrays.
IEEE Trans. Acoust. Speech Signal Process.
John V. McCanny, John G. McWhirter, Sun-Yuan Kung
1990 Misc conf
VLSI architectures for digital image coding.
ICASSP
M. Yan, John V. McCanny, Yi Hu
1989 Misc conf
A bit-level systolic architecture for very high performance IIR filters.
ICASSP
Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny
1989 J jnl
Bit-Level systolic architectures for high performance IIR filtering.
J. VLSI Signal Process.
Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny
1988 Misc conf
An independent evaluation of the performance of the CCITT G.722 wideband coding recommendation using music signals.
ICASSP
S. M. F. Smyth, John V. McCanny, P. Challener
1988 Misc conf
An independent evaluation of the performance of the CCITT G.722 wideband coding recommendation.
ICASSP
S. M. F. Smyth, John V. McCanny, P. Challener
1988 Misc conf
Systolic IIR filters with bit level pipelining.
ICASSP
Roger F. Woods, Simon C. Knowles, John V. McCanny, John G. McWhirter
1987 J jnl
Some Systolic Array Developments in the United Kingdom.
Computer
John V. McCanny, John G. McWhirter
1987 — conf
Transformed sub-band coding of speech using vector quantization.
ECST
H. A. Kaouri, John V. McCanny
1986 Misc conf
A high speed CMOS/SOS implementation of a bit level systolic correlator.
ICASSP
J. C. White, John V. McCanny, A. McCabe, John G. McWhirter, R. Evans
1986 Misc conf
Mapping system level functions on to bit level systolic arrays.
ICASSP
John V. McCanny
1985 Misc conf
A systolic implementation of the Winograd Fourier transform algorithm.
ICASSP
J. S. Ward, John V. McCanny, John G. McWhirter