John Reuben

22 papers C 1Journal 9Unranked 11
YearRankTypeTitle / Venue / Authors
2025 J jnl
In-Memory Implementation of an Approximate Adder With Reduced Latency and Error.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vijaya Lakshmi, Vikramkumar Pudi, John Reuben
2025 — conf
Multiplier-Free In-Memory Vector-Matrix Multiplication Using Distributed Arithmetic.
MCSoC
Felix Zeller, John Reuben, Dietmar Fey
2025 J jnl
Multiplier-free In-Memory Vector-Matrix Multiplication Using Distributed Arithmetic.
CoRR
Felix Zeller, John Reuben, Dietmar Fey
2025 C conf
Smart Sensing of Multi-bit Resistive Memory using a Single Reference.
DSD
John Reuben, Dietmar Fey
2025 — conf
Using a SystemC Based Design and Simulation System for Hyperdimensional Computing with Multi-Level-Cell Look-Up-Tables with ReRAM.
MetroXRAINE
Benjamin Seiler, John Reuben, Dietmar Fey
2024 — conf
On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory.
NorCAS
John Reuben, Suzanne Lancaster, Dietmar Fey, Stefan Slesazeck
2023 — conf
A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories.
MOCAST
John Reuben, Dietmar Fey, Stefan Slesazeck
2023 — conf
Hyper Dimensional Computing with Ferroelectric Tunneling Junctions.
NANOARCH
Stefan Slesazeck, Suzanne Lancaster, John Reuben, Shima Hosseinzadeh, Dietmar Fey, Thomas Mikolajick
2022 J jnl
A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vijaya Lakshmi, John Reuben, Vikramkumar Pudi
2022 J jnl
Inner Product Computation In-Memory Using Distributed Arithmetic.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vijaya Lakshmi, Vikramkumar Pudi, John Reuben
2021 J jnl
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates.
IEEE Trans. Very Large Scale Integr. Syst.
John Reuben, Stefan Pechmann
2021 — conf
Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles.
ISVLSI
John Reuben, Dietmar Fey
2021 — conf
Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic.
ICECS
Dietmar Fey, John Reuben, Stefan Slesazeck
2020 — conf
A Parallel-friendly Majority Gate to Accelerate In-memory Computation.
ASAP
John Reuben, Stefan Pechmann
2020 — conf
Direct state transfer in MLC based memristive ReRAM devices for ternary computing.
ECCTD
Dietmar Fey, John Reuben
2019 — ch.
A Taxonomy and Evaluation Framework for Memristive Logic.
Handbook of Memristor Networks
John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2019 — conf
A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM.
NORCAS
John Reuben, Dietmar Fey
2017 — conf
Memristive logic: A framework for evaluation and comparison.
PATMOS
John Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2016 J jnl
Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.
J. Circuits Syst. Comput.
Kamineni Sumanth Kumar, John Reuben
2014 J jnl
A novel clock generation algorithm for system-on-chip based on least common multiple.
Comput. Electr. Eng.
John Reuben, Harish M. Kittur, Mohd Shoaib
2014 J jnl
Low Power fractional-n frequency Divider with Improved Resolution.
J. Circuits Syst. Comput.
V. Mohammed Zackriya, John Reuben, Ashim Harsh, Harish M. Kittur
2013 J jnl
Capacitance driven clock mesh synthesis to minimize skew and power dissipation.
IEICE Electron. Express
John Reuben, V. Mohammed Zackriya, Salma Nashit, Harish M. Kittur