John Paul Shen

144 papers A* 36A 13B 3C 9Misc 2Journal 49Unranked 32

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A-Graph: A Unified Graph Representation for At-Will Simulation across System Stacks. CoRR Daniel Price, Prabhu Vellaisamy, Patricia Gonzalez, George Michelogiannakis, John Paul Shen, Di Wu
2026	J	`jnl`	Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators. CoRR Prabhu Vellaisamy, Harideep Nair, Di Wu, R. D. (Shawn) Blanton, John Paul Shen
2026	—	`conf`	Mugi: Value Level Parallelism For Efficient LLMs. ASPLOS (2) Daniel Price, Prabhu Vellaisamy, John Paul Shen, Di Wu
2026	J	`jnl`	Mugi: Value Level Parallelism For Efficient LLMs. CoRR Daniel Price, Prabhu Vellaisamy, John Paul Shen, Di Wu
2026	J	`jnl`	NeuroAI Temporal Neural Networks (NeuTNNs): Microarchitecture and Design Framework for Specialized Neuromorphic Processing Units. CoRR Shanmuga Venkatachalam, Prabhu Vellaisamy, Harideep Nair, Wei-Che Huang, YoungSeok Na, Yuyang Kang, Quinn Jacobson, John Paul Shen
2026	J	`jnl`	NeuroHex: Highly-Efficient Hex Coordinate System for Creating World Models to Enable Adaptive AI. CoRR Quinn Jacobson, Joe Luo, Jingfei Xu, Shanmuga Venkatachalam, Kevin Wang, Dingchao Rong, John Paul Shen
2026	J	`jnl`	TaxBreak: Unmasking the Hidden Costs of LLM Inference Through Overhead Decomposition. CoRR Prabhu Vellaisamy, Shreesh Tripathi, Vignesh Natarajan, Surya Santhan Thenarasu, R. D. (Shawn) Blanton, John Paul Shen
2025	—	`conf`	Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks. ISVLSI Devon Lister, Prabhu Vellaisamy, John Paul Shen, Di Wu
2025	J	`jnl`	Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks. CoRR Devon Lister, Prabhu Vellaisamy, John Paul Shen, Di Wu
2025	B	`conf`	Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures. ISPASS Prabhu Vellaisamy, Thomas Labonte, Sourav Chakraborty, Matt Turner, Samantika Sury, John Paul Shen
2025	J	`jnl`	Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures. CoRR Prabhu Vellaisamy, Thomas Labonte, Sourav Chakraborty, Matt Turner, Samantika Sury, John Paul Shen
2025	A	`conf`	Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs. DATE Prabhu Vellaisamy, Harideep Nair, Thomas Kang, Yichen Ni, Haoyang Fan, Bin Qi, Jeff Chen, R. D. Shawn Blanton, John Paul Shen
2024	C	`conf`	Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference. VLSI-SoC Harideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen
2024	J	`jnl`	Corrigendum: SemNet: Learning semantic attributes for human activity recognition with deep belief networks. Frontiers Big Data Shanmuga Venkatachalam, Harideep Nair, Ming Zeng, Cathy Tan, Ole J. Mengshoel, John Paul Shen
2024	—	`conf`	Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators. ISVLSI Prabhu Vellaisamy, Harideep Nair, Di Wu, R. D. Shawn Blanton, John Paul Shen
2024	—	`conf`	NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors. NICE Harideep Nair, William Leyman, Agastya Sampath, Quinn Jacobson, John Paul Shen
2024	J	`jnl`	NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors. CoRR Harideep Nair, William Leyman, Agastya Sampath, Quinn Jacobson, John Paul Shen
2024	J	`jnl`	OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference. CoRR Harideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen
2024	—	`conf`	Realtime Person Identification via Gait Analysis Using IMU Sensors on Edge Devices. ICONS Shanmuga Venkatachalam, Harideep Nair, Prabhu Vellaisamy, Yongqi Zhou, Ziad Youssfi, John Paul Shen
2024	J	`jnl`	Realtime Person Identification via Gait Analysis. CoRR Shanmuga Venkatachalam, Harideep Nair, Prabhu Vellaisamy, Yongqi Zhou, Ziad Youssfi, John Paul Shen
2024	—	`conf`	TNN-CIM: An In-SRAM CMOS Implementation of TNN-Based Synaptic Arrays with STDP Learning. AICAS Harideep Nair, David Barajas-Jasso, Quinn Jacobson, John Paul Shen
2024	J	`jnl`	TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering. CoRR Prabhu Vellaisamy, Harideep Nair, Vamsikrishna Ratnakaram, Dhruv Gupta, John Paul Shen
2024	J	`jnl`	TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering. IEEE Trans. Circuits Syst. II Express Briefs Prabhu Vellaisamy, Harideep Nair, Vamsikrishna Ratnakaram, Dhruv Gupta, John Paul Shen
2024	J	`jnl`	Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs. CoRR Prabhu Vellaisamy, Harideep Nair, Thomas Kang, Yichen Ni, Haoyang Fan, Bin Qi, Jeff Chen, R. D. Shawn Blanton, John Paul Shen
2024	J	`jnl`	tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low-Precision Edge AI. CoRR Harideep Nair, Prabhu Vellaisamy, Albert Chen, Joseph Finn, Anna Li, Manav Trivedi, John Paul Shen
2024	J	`jnl`	tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. CoRR Prabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry H. Wang, R. D. (Shawn) Blanton, John Paul Shen
2023	J	`jnl`	IDIoT: Multimodal Framework for Ubiquitous Identification and Assignment of Human-carried Wearable Devices. ACM Trans. Internet Things Adeola Bannis, Shijia Pan, Carlos Ruiz Dominguez, John Paul Shen, Hae Young Noh, Pei Zhang
2023	C	`conf`	tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low-Precision Edge AI. ISCAS Harideep Nair, Prabhu Vellaisamy, Albert Chen, Joseph Finn, Anna Li, Manav Trivedi, John Paul Shen
2023	—	`conf`	tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. ISVLSI Prabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen
2022	J	`jnl`	SemNet: Learning semantic attributes for human activity recognition with deep belief networks. Frontiers Big Data Shanmuga Venkatachalam, Harideep Nair, Ming Zeng, Cathy Tan, Ole J. Mengshoel, John Paul Shen
2022	—	`conf`	TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs. ISVLSI Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen
2022	J	`jnl`	TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs. CoRR Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen
2022	J	`jnl`	Towards a Design Framework for TNN-Based Neuromorphic Sensory Processing Units. CoRR Prabhu Vellaisamy, John Paul Shen
2021	—	`conf`	A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks. ISVLSI Harideep Nair, John Paul Shen, James E. Smith
2021	J	`jnl`	A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks. CoRR Harideep Nair, John Paul Shen, James E. Smith
2021	Misc	`conf`	Unsupervised Clustering of Time Series Signals Using Neuromorphic Energy-Efficient Temporal Neural Networks. ICASSP Shreyas Chaudhari, Harideep Nair, José M. F. Moura, John Paul Shen
2021	J	`jnl`	Unsupervised Clustering of Time Series Signals using Neuromorphic Energy-Efficient Temporal Neural Networks. CoRR Shreyas Chaudhari, Harideep Nair, José M. F. Moura, John Paul Shen
2020	J	`jnl`	Direct CMOS Implementation of Neuromorphic Temporal Neural Networks for Sensory Processing. CoRR Harideep Nair, John Paul Shen, James E. Smith
2020	J	`jnl`	Generating Realistic Ride-Hailing Datasets Using GANs. ACM Trans. Spatial Algorithms Syst. Abhinav Jauhri, Brad Stocks, Jian-Hui Li, Koichi Yamada, John Paul Shen
2020	—	`conf`	Sky Segmentation for Enhanced Depth Reconstruction and Bokeh Rendering with Efficient Architectures. Computational Imaging Tyler Nuanes, Matt Elsey, Radek Grzeszczuk, John Paul Shen
2019	—	`conf`	AttriNet: learning mid-level features for human activity recognition with deep belief networks. UbiComp/ISWC Adjunct Harideep Nair, Cathy Tan, Ming Zeng, Ole J. Mengshoel, John Paul Shen
2019	—	`conf`	Audio-visual TED corpus: enhancing the TED-LIUM corpus with facial information, contextual text and object recognition. UbiComp/ISWC Adjunct Guan-Lin Chao, Chih Chi Hu, Bing Liu, John Paul Shen, Ian R. Lane
2019	—	`conf`	Deep Speaker Embedding for Speaker-Targeted Automatic Speech Recognition. NLPIR Guan-Lin Chao, John Paul Shen, Ian R. Lane
2018	—	`conf`	Improving Bag-Of-Words: Capturing Local Information for Motion-Based Activity Recognition. UbiComp/ISWC Adjunct Ming Zeng, Tong Yu, Ole J. Mengshoel, Helen Qin, Chris Lee, John Paul Shen
2017	—	`conf`	Data Driven Analysis of the Potentials of Dynamic Ride Pooling. IWCTS@SIGSPATIAL Min Hao Chen, Abhinav Jauhri, John Paul Shen
2017	J	`jnl`	On the Real-time Vehicle Placement Problem. CoRR Abhinav Jauhri, Carlee Joe-Wong, John Paul Shen
2017	—	`conf`	Space-Time Graph Modeling of Ride Requests Based on Real-World Data. AAAI Workshops Abhinav Jauhri, Brian Foo, Jérôme Berclaz, Chih Chi Hu, Radek Grzeszczuk, Vasu Parameswaran, John Paul Shen
2017	J	`jnl`	Space-Time Graph Modeling of Ride Requests Based on Real-World Data. CoRR Abhinav Jauhri, Brian Foo, Jérôme Berclaz, Chih Chi Hu, Radek Grzeszczuk, Vasu Parameswaran, John Paul Shen
2017	—	`conf`	SurfaceVibe: vibration-based tap & swipe tracking on ubiquitous surfaces. IPSN Shijia Pan, Ceferino Gabriel Ramirez, Mostafa Mirshekari, Jonathon Fagert, Albert Jin Chung, Chih Chi Hu, John Paul Shen, Hae Young Noh, Pei Zhang
2008	J	`jnl`	Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Trans. Parallel Distributed Syst. Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen
2006	A*	`conf`	Die Stacking (3D) Microarchitecture. MICRO Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb
2006	A*	`conf`	Multiple Instruction Stream Processor. ISCA Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan N. Rakvic, Hong Wang, John Paul Shen
2006	A*	`ed.`	Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006 ASPLOS John Paul Shen, Margaret Martonosi
2005	A	`conf`	A Dependency Chain Clustered Microarchitecture. IPDPS Satish Narayanasamy, Hong Wang, Perry H. Wang, John Paul Shen, Brad Calder
2005	A*	`conf`	Mitigating Amdahl's Law through EPI Throttling. ISCA Murali Annavaram, Ed Grochowski, John Paul Shen
2004	J	`jnl`	A case for shared instruction cache on chip multiprocessors running OLTP. SIGARCH Comput. Archit. News Partha Kundu, Murali Annavaram, Trung A. Diep, John Paul Shen
2004	C	`conf`	Best of Both Latency and Throughput. ICCD Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
2004	A*	`conf`	Hardware Support for Prescient Instruction Prefetch. HPCA Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen
2004	J	`jnl`	Helper Threads via Virtual Multithreading. IEEE Micro Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
2004	A*	`conf`	Helper threads via virtual multithreading on an experimental itanium ASPLOS Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
2004	A	`conf`	Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. CGO Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar, John Paul Shen
2003	A*	`conf`	A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
2003	A*	`conf`	Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice. MICRO Richard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen
2002	C	`conf`	Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors. ICCD Murali Annavaram, Trung A. Diep, John Paul Shen
2002	A*	`conf`	Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. HPCA Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen
2002	A*	`conf`	Non-Vital Loads. HPCA Ryan N. Rakvic, Bryan Black, Deepak Limaye, John Paul Shen
2002	A*	`conf`	Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. PLDI Shih-Wei Liao, Perry H. Wang, Hong Wang, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery
2002	—	`conf`	Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. Interaction between Compilers and Computer Architectures R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen
2001	C	`conf`	Clear and Present Tensions in Microprocessor Design. ICCD John Paul Shen
2001	J	`jnl`	Coming challenges in microarchitecture and architecture. Proc. IEEE Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen
2001	A*	`conf`	Dynamic speculative precomputation. MICRO Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen
2001	C	`conf`	Parallel Cachelets. ICCD Deepak Limaye, Ryan N. Rakvic, John Paul Shen
2001	A*	`conf`	Register Renaming and Scheduling for Dynamic Execution of Predicated Code. HPCA Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen
2001	—	`conf`	Relating buffer-oriented microarchitecture validation to high-level pipeline functionality. HLDVT Noppanunt Utamaphethai, Ronald D. Blanton, John Paul Shen
2001	A*	`conf`	Speculative precomputation: long-range prefetching of delinquent loads. ISCA Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
2000	J	`jnl`	A Buffer-Oriented Methodology for Microarchitecture Validation. J. Electron. Test. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
2000	A*	`conf`	Completion time multiple branch prediction for enhancing trace cache performance. ISCA Ryan N. Rakvic, Bryan Black, John Paul Shen
2000	J	`jnl`	Effectiveness of Microarchitecture Test Program Generation. IEEE Des. Test Comput. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
2000	A*	`conf`	Instruction path coprocessors. ISCA Yuan C. Chou, John Paul Shen
2000	A*	`conf`	PipeRench implementation of the instruction path coprocessor. MICRO Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen
1999	J	`jnl`	An integrated functional performance simulator. IEEE Micro Candice Bechem, Jonathan Combs, Noppanunt Utamaphethai, Bryan Black, R. D. (Shawn) Blanton, John Paul Shen
1999	—	`conf`	Mispredicted Path Cache Effects. Euro-Par Jonathan Combs, Candice Bechem Combs, John Paul Shen
1999	A	`conf`	Reducing branch misprediction penalties via dynamic control independence detection. International Conference on Supercomputing Yuan C. Chou, Jason Fung, John Paul Shen
1999	Misc	`conf`	Superscalar Processor Validation at the Microarchitecture Level. VLSI Design Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
1999	A	`conf`	System-Level Issues for Software Thread Integration: Guest Triggering and Host Selection. RTSS Alexander G. Dean, John Paul Shen
1999	A*	`conf`	The Block-Based Trace Cache. ISCA Bryan Black, Bohuslav Rychlik, John Paul Shen
1998	J	`jnl`	Calibration of Microprocessor Performance Models. Computer Bryan Black, John Paul Shen
1998	—	`conf`	Efficacy and Performance Impact of Value Prediction. IEEE PACT Bohuslav Rychlik, John Faistl, Bryon Krug, John Paul Shen
1998	J	`jnl`	Exploiting Value Locality to Exceed the Dataflow Limit. Int. J. Parallel Program. Mikko H. Lipasti, John Paul Shen
1998	—	`conf`	Hardware to Software Migration with Real-Time Thread Integration. EUROMICRO Alexander G. Dean, John Paul Shen
1998	A	`conf`	Load Execution Latency Reduction. International Conference on Supercomputing Bryan Black, Brian Mueller, Stephanie Postal, Ryan N. Rakvic, Noppanunt Utamaphethai, John Paul Shen
1998	A	`conf`	Techniques for Software Thread Integration in Real-Time Embedded Systems. RTSS Alexander G. Dean, John Paul Shen
1997	A*	`conf`	A Framework for Statistical Modeling of Superscalar Processor Performance. HPCA Derek B. Noonburg, John Paul Shen
1997	—	`conf`	A Realistic Study on Multithreaded Superscalar Processor Design. Euro-Par Yuan C. Chou, Daniel P. Siewiorek, John Paul Shen
1997	—	`conf`	Compiler Support for Low-Cost Synchronization Among Threads. PARCO Chris J. Newburn, John Paul Shen
1997	J	`jnl`	Post-pass partitioning of signal processing programs. Int. J. Parallel Program. Chris J. Newburn, John Paul Shen
1997	J	`jnl`	Superspeculative Microarchitecture for Beyond AD 2000. Computer Mikko H. Lipasti, John Paul Shen
1997	—	`conf`	The Performance Potential of Value and Dependence Prediction. Euro-Par Mikko H. Lipasti, John Paul Shen
1996	—	`conf`	Automatic partitioning of signal processing programs for symmetric multiprocessors. IEEE PACT Chris J. Newburn, John Paul Shen
1996	C	`conf`	Can Trace-Driven Simulators Accurately Predict Superscalar Performance? ICCD Bryan Black, Andrew S. Huang, Mikko H. Lipasti, John Paul Shen
1996	A*	`conf`	Exceeding the Dataflow Limit via Value Prediction. MICRO Mikko H. Lipasti, John Paul Shen
1996	A*	`conf`	The Intrinsic Bandwidth Requirements of Ordinary Programs. ASPLOS Andrew S. Huang, John Paul Shen
1996	A*	`conf`	Value Locality and Load Value Prediction. ASPLOS Mikko H. Lipasti, Christopher B. Wilkerson, John Paul Shen
1995	A*	`conf`	A limit study of local memory requirements using value reuse profiles. MICRO Andrew S. Huang, John Paul Shen
1995	A*	`conf`	Performance Evaluation of the PowerPC 620 Microarchitecture. ISCA Trung A. Diep, Christopher Nelson, John Paul Shen
1995	—	`conf`	Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures. FTCS Trung A. Diep, John Paul Shen
1995	J	`jnl`	VMW: A Visualization-Based Microarchitecture Workbench. Computer Trung A. Diep, John Paul Shen
1994	—	`conf`	A PDG-based Tool and its Use in Analyzing Program Control Dependences. IFIP PACT Chris J. Newburn, Derek B. Noonburg, John Paul Shen
1994	J	`jnl`	Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring. IEEE Trans. Computers Michael A. Schuette, John Paul Shen
1994	A*	`conf`	Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. ISCA Andrew S. Huang, Gert Slavenburg, John Paul Shen
1994	A*	`conf`	Theoretical modeling of superscalar processor performance. MICRO Derek B. Noonburg, John Paul Shen
1993	C	`conf`	Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000. ICCD Trung A. Diep, Mikko H. Lipasti, John Paul Shen
1993	—	`conf`	Balancing Fine- and Medium-Grained Parallelism in Scheduling Loops for the XIMD Architecture. Architectures and Compilation Techniques for Fine and Medium Grain Parallelism Chris J. Newburn, Andrew S. Huang, John Paul Shen
1993	A*	`conf`	EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors. MICRO Trung A. Diep, John Paul Shen, Mike Phillip
1993	J	`jnl`	Instruction-level experimental evaluation of the Multiflow TRACE 14/300 VLIW computer. J. Supercomput. Michael A. Schuette, John Paul Shen
1992	—	`conf`	Direct Methods for Synthesis of Self-Monitoring State Machines. FTCS Scott H. Robinson, John Paul Shen
1991	A*	`conf`	A Variable Instruction Stream Extension to the VLIW Architecture. ASPLOS Andrew Wolfe, John Paul Shen
1991	A*	`conf`	An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300. MICRO Michael A. Schuette, John Paul Shen
1991	—	`conf`	Exploiting Instruction-Level Resource Parallelism for Transparent, Integrated Control-Flow Monitoring. FTCS Michael A. Schuette, John Paul Shen
1991	A*	`conf`	Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. MICRO Maurício Breternitz Jr., John Paul Shen
1991	A*	`conf`	Instruction Level Profiling and Evaluation of the IBM/6000. ISCA Chriss Stephens, Bryce Cogswell, John Heinlein, Gregory Palmer, John Paul Shen
1990	A*	`conf`	Architecture Synthesis of High-Performance Application-Specific Processors. DAC Maurício Breternitz Jr., John Paul Shen
1990	J	`jnl`	Continuous signature monitoring: low-cost concurrent detection of processor control errors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kent D. Wilken, John Paul Shen
1990	A	`conf`	Evaluation and Synthesis of Self-Monitoring State Machines. ICCAD Scott H. Robinson, John Paul Shen
1988	J	`jnl`	A CMOS fault extractor for inductive fault analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. F. Joel Ferguson, John Paul Shen
1988	A	`conf`	Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control Errors. ITC Kent D. Wilken, John Paul Shen
1988	A	`conf`	Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. ITC John Paul Shen, F. Joel Ferguson
1988	A*	`conf`	Flexible processors: a promising application-specific processor design approach. MICRO Andrew Wolfe, John Paul Shen
1988	A*	`conf`	Organization of array data for concurrent memory access. MICRO Maurício Breternitz Jr., John Paul Shen
1988	A*	`conf`	The White Dwarf: A High-Performance Application-Specific Processor. ISCA Andrew Wolfe, Maurício Breternitz Jr., Chriss Stephens, A. L. Ting, David Blair Kirk, Ronald P. Bianchini Jr., John Paul Shen
1987	J	`jnl`	Interprocessor Traffic Scheduling Algorithm for Multiple-Processor Networks. IEEE Trans. Computers Ronald P. Bianchini Jr., John Paul Shen
1987	J	`jnl`	Processor Control Flow Monitoring Using Signatured Instruction Streams. IEEE Trans. Computers Michael A. Schuette, John Paul Shen
1986	J	`jnl`	Fault-tolerance and performance analysis of beta-networks. Parallel Comput. John Paul Shen, John P. Hayes, Luigi Ciminiera, Angelo Serra
1986	—	`conf`	Highlights of CMU Research on CAD, CAM, CAT of VLSI Circuits. FJCC John Paul Shen
1985	A	`conf`	Automated Design for Testability of Semicustom Integrated Circuits. ITC Patrick P. Fasang, Michael A. Schuette, John Paul Shen, William A. Gwaltney
1985	J	`jnl`	Inductive Fault Analysis of MOS Integrated Circuits. IEEE Des. Test John Paul Shen, Wojciech Maly, F. Joel Ferguson
1984	J	`jnl`	Fault-Tolerance of Dynamic-Full-Access Interconnection Networks. IEEE Trans. Computers John Paul Shen, John P. Hayes
1984	A	`conf`	Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. ITC Wojciech Maly, F. Joel Ferguson, John Paul Shen
1984	J	`jnl`	The Design of Easily Tastabel VLSI Array Multipliers. IEEE Trans. Computers John Paul Shen, F. Joel Ferguson
1983	B	`conf`	Easily-Testable (N, K) Shuffle/Exchange Networks. ICPP David C. H. Lee, John Paul Shen
1983	A	`conf`	On-Line Self-Monitoring Using Signatured Instruction Streams. ITC Michael A. Schuette, John Paul Shen
1983	C	`conf`	The design of two easily-testable VLSI array multipliers. IEEE Symposium on Computer Arithmetic F. Joel Ferguson, John Paul Shen
1982	B	`conf`	Fault tolerance analysis of several interconnection networks. ICPP John Paul Shen
1980	A*	`conf`	Fault Tolerance of a Class of Connecting Networks. ISCA John Paul Shen, John P. Hayes