John P. Hayes

269 papers A* 18A 42B 10C 19Misc 10Journal 120Unranked 48
YearRankTypeTitle / Venue / Authors
2026 J jnl
BASE: A Framework for Treating Errors in Stochastic Computing Systems.
IEEE Trans. Computers
Timothy J. Baker, John P. Hayes
2026 J jnl
Runtime Termination Control in Stochastic Computing.
IEEE Trans. Emerg. Top. Comput.
Owen Hoffend, John P. Hayes
2025 J jnl
Comparative Analysis of Error Tolerance and Hardware Efficiency in Stochastic Computing-based Digital Filters.
J. Circuits Syst. Comput.
Roshwin Sengupta, Ilia Polian, John P. Hayes
2025 — conf
Fault-Tolerant and Low-Latency Stochastic Neural Networks via Adaptive Bitstream Precision.
ATS
Roshwin Sengupta, John P. Hayes, Ilia Polian
2025 C conf
Low-Power Continuous Wavelet Transform Employing Stochastic Computing.
ISCAS
Roshwin Sengupta, Ilia Polian, John P. Hayes
2025 J jnl
WASENN: Wavelet Assisted Stochastic Enabled Neural Network for Human Activity Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Roshwin Sengupta, Ilia Polian, John P. Hayes
2024 — conf
Fault Tolerance in Stochastic Circuits for Recurrent Sequential Neural Networks.
ATS
Roshwin Sengupta, Ilia Polian, John P. Hayes
2024 C conf
Performance and Error Tolerance of Stochastic Computing-Based Digital Filter Design.
DDECS
Roshwin Sengupta, Ilia Polian, John P. Hayes
2023 A conf
Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior.
DATE
Timothy J. Baker, John P. Hayes
2023 — conf
Mitigating the Correlation Problem in Multi-Layer Stochastic Circuits.
ICRC
Owen Hoffend, John P. Hayes
2023 — conf
Stochastic Computing as a Defence Against Adversarial Attacks.
DSN-W
Florian Neugebauer, Vivek Vekariya, Ilia Polian, John P. Hayes
2022 C conf
Analyzing Multilevel Stochastic Circuits using Correlation Matrices.
DDECS
Owen Hoffend, John P. Hayes
2022 J jnl
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design.
ACM Trans. Design Autom. Electr. Syst.
Timothy J. Baker, John P. Hayes
2022 — conf
Multiplexer-Majority Chains: Managing Correlation and Cost in Stochastic Number Generation.
NANOARCH
Timothy J. Baker, Owen Hoffend, John P. Hayes
2022 C conf
Stochastic Computing Architectures for Lightweight LSTM Neural Networks.
DDECS
Roshwin Sengupta, Ilia Polian, John P. Hayes
2022 C conf
Wavelet Transform Assisted Neural Networks for Human Activity Recognition.
ISCAS
Roshwin Sengupta, Ilia Polian, John P. Hayes
2021 — conf
Benefits of Stochastic Computing in Hearing Aid Filterbank Design.
BioCAS
Timothy J. Baker, Yiqiu Sun, John P. Hayes
2021 J jnl
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design.
CoRR
Timothy J. Baker, John P. Hayes
2021 J jnl
Guest Editors' Introduction: Stochastic Computing for Neuromorphic Applications.
IEEE Des. Test
Ilia Polian, John P. Hayes, Vincent T. Lee, Weikang Qian
2020 A conf
Bayesian Accuracy Analysis of Stochastic Circuits.
ICCAD
Timothy J. Baker, John P. Hayes
2020 A conf
Exploring Target Function Approximation for Stochastic Circuit Minimization.
ICCAD
Chen Wang, Weihua Xiao, John P. Hayes, Weikang Qian
2020 C conf
Hardware-based Fast Real-time Image Classification with Stochastic Computing.
ICCD
Ponnanna Kelettira Muthappa, Florian Neugebauer, Ilia Polian, John P. Hayes
2020 — conf
Retraining and Regularization to Optimize Neural Networks for Stochastic Computing.
ISVLSI
Junseok Oh, Florian Neugebauer, Ilia Polian, John P. Hayes
2020 A conf
The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing.
DATE
Timothy J. Baker, John P. Hayes
2019 J jnl
Equivalence Among Stochastic Logic Circuits and its Application to Synthesis.
IEEE Trans. Emerg. Top. Comput.
Te-Hsuan Chen, John P. Hayes
2019 A conf
Exploiting Randomness in Stochastic Computing.
ICCAD
Pai-Shun Ting, John P. Hayes
2019 — conf
Impact of Autocorrelation on Stochastic Circuit Accuracy.
ISVLSI
Timothy J. Baker, John P. Hayes
2019 — conf
On the Limits of Stochastic Computing.
ICRC
Florian Neugebauer, Ilia Polian, John P. Hayes
2019 — conf
On the maximum function in stochastic computing.
CF
Florian Neugebauer, Ilia Polian, John P. Hayes
2019 J jnl
Removing constant-induced errors in stochastic circuits.
IET Comput. Digit. Tech.
Pai-Shun Ting, John P. Hayes
2018 J jnl
A comparison of perspectives of Kuwaiti and Indonesian residents towards e-government.
Electron. Gov. an Int. J.
Dinesh A. Mirchandani, Yunus Kathawala, Julius H. Johnson Jr., John P. Hayes, Sudhir Chawla
2018 J jnl
Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design.
ACM J. Emerg. Technol. Comput. Syst.
Florian Neugebauer, Ilia Polian, John P. Hayes
2018 — conf
Maxflow: Minimizing Latency in Hybrid Stochastic-Binary Systems.
ACM Great Lakes Symposium on VLSI
Pai-Shun Ting, John P. Hayes
2018 J jnl
S-box-based random number generation for stochastic computing.
Microprocess. Microsystems
Florian Neugebauer, Ilia Polian, John P. Hayes
2018 J jnl
The Promise and Challenge of Stochastic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Armin Alaghi, Weikang Qian, John P. Hayes
2017 — conf
Achieving progressive precision in stochastic computing.
GlobalSIP
Te-Hsuan Chen, Pai-Shun Ting, John P. Hayes
2017 C conf
Building a Better Random Number Generator for Stochastic Computing.
DSD
Florian Neugebauer, Ilia Polian, John P. Hayes
2017 A conf
Design of accurate stochastic number generators with noisy emerging devices for stochastic computing.
ICCAD
Meng Yang, John P. Hayes, Deliang Fan, Weikang Qian
2017 — conf
Eliminating a hidden error source in stochastic circuits.
DFT
Pai-Shun Ting, John P. Hayes
2017 J jnl
Energy-Efficient Hybrid Stochastic-Binary Neural Networks for Near-Sensor Computing.
CoRR
Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze
2017 A conf
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing.
DATE
Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze
2017 A conf
Framework for quantifying and managing accuracy in stochastic circuit design.
DATE
Florian Neugebauer, Ilia Polian, John P. Hayes
2017 — conf
On the Role of Sequential Circuits in Stochastic Computing.
ACM Great Lakes Symposium on VLSI
Pai-Shun Ting, John P. Hayes
2017 J jnl
Trading Accuracy for Energy in Stochastic Circuit Design.
ACM J. Emerg. Technol. Comput. Syst.
Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li
2016 — conf
Design of Division Circuits for Stochastic Computing.
ISVLSI
Te-Hsuan Chen, John P. Hayes
2016 C conf
Isolation-based decorrelation of stochastic circuits.
ICCD
Pai-Shun Ting, John P. Hayes
2015 — conf
Dimension reduction in statistical simulation of digital circuits.
SpringSim (TMS-DEVS)
Armin Alaghi, John P. Hayes
2015 A* conf
Equivalence among stochastic logic circuits and its application.
DAC
Te-Hsuan Chen, John P. Hayes
2015 A* conf
Introduction to stochastic computing and its challenges.
DAC
John P. Hayes
2015 C conf
Low-Area and High-Speed Approximate Matrix-Vector Multiplier.
DDECS
I-Che Chen, John P. Hayes
2015 — conf
On the Functions Realized by Stochastic Computing Circuits.
ACM Great Lakes Symposium on VLSI
Armin Alaghi, John P. Hayes
2015 A conf
Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs.
ICCAD
Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li
2015 J jnl
STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Armin Alaghi, John P. Hayes
2014 C conf
Analyzing and controlling accuracy in stochastic circuits.
ICCD
Te-Hsuan Chen, John P. Hayes
2014 J jnl
Behavior of stochastic circuits under severe error conditions.
it Inf. Technol.
Te-Hsuan Chen, Armin Alaghi, John P. Hayes
2014 A conf
Fast and accurate computation using stochastic circuits.
DATE
Armin Alaghi, John P. Hayes
2013 — conf
Approximate simulation of circuits with probabilistic behavior.
DFTS
Alexandru Paler, Josef Kinseher, Ilia Polian, John P. Hayes
2013 C conf
Design of stochastic Viterbi decoders for convolutional codes.
DDECS
Te-Hsuan Chen, John P. Hayes
2013 — book
Design, Analysis and Test of Logic Circuits Under Uncertainty
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
2013 C conf
Exploiting correlation in stochastic circuit design.
ICCD
Armin Alaghi, John P. Hayes
2013 A* conf
Stochastic circuits for real-time image-processing applications.
DAC
Armin Alaghi, Cheng Li, John P. Hayes
2013 J jnl
Survey of Stochastic Computing.
ACM Trans. Embed. Comput. Syst.
Armin Alaghi, John P. Hayes
2012 C conf
A spectral transform approach to stochastic circuits.
ICCD
Armin Alaghi, John P. Hayes
2012 — conf
Detection and diagnosis of faulty quantum circuits.
ASP-DAC
Alexandru Paler, Ilia Polian, John P. Hayes
2012 J jnl
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems.
ACM Trans. Reconfigurable Technol. Syst.
Kenneth M. Zick, John P. Hayes
2012 J jnl
Robust Coupling Delay Test Sets.
J. Electron. Test.
Joonhwan Yi, John P. Hayes
2012 A conf
Scalable sampling methodology for logic simulation: Reduced-Ordered Monte Carlo.
ICCAD
Chien-Chih Yu, Armin Alaghi, John P. Hayes
2011 — conf
A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits.
A-SSCC
Dae Young Lee, David D. Wentzloff, John P. Hayes
2011 J jnl
Modeling and Mitigating Transient Errors in Logic Circuits.
IEEE Trans. Dependable Secur. Comput.
Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker
2011 J jnl
Selective Hardening: Toward Cost-Effective Error Tolerance.
IEEE Des. Test Comput.
Ilia Polian, John P. Hayes
2011 B conf
Tomographic Testing and Validation of Probabilistic Circuits.
ETS
Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes
2011 A conf
Trigonometric method to handle realistic error probabilities in logic circuits.
DATE
Chien-Chih Yu, John P. Hayes
2011 C conf
Wireless wafer-level testing of integrated circuits via capacitively-coupled channels.
DDECS
Dae Young Lee, David D. Wentzloff, John P. Hayes
2010 — conf
Advanced modeling of faults in Reversible circuits.
EWDTS
Ilia Polian, John P. Hayes
2010 A conf
On-line sensing for healthier FPGA systems.
FPGA
Kenneth M. Zick, John P. Hayes
2010 Misc conf
Scalable and accurate estimation of probabilistic behavior in sequential circuits.
VTS
Chien-Chih Yu, John P. Hayes
2010 B conf
Self-Test and Adaptation for Random Variations in Reliability.
FPL
Kenneth M. Zick, John P. Hayes
2010 — conf
Toward Physically-Adaptive Computing.
SASO
Kenneth M. Zick, John P. Hayes
2009 A conf
Contactless testing: Possibility or pipe-dream?
DATE
Erik Jan Marinissen, Dae Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol
2009 A* conf
Improving testability and soft-error resilience through retiming.
DAC
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
2009 C conf
On-line characterization and reconfiguration for single event upset variations.
IOLTS
Kenneth M. Zick, John P. Hayes
2009 — book
Quantum Circuit Simulation.
George F. Viamontes, Igor L. Markov, John P. Hayes
2009 J jnl
Signature-Based SER Analysis and Design of Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes
2008 — conf
High-level vulnerability over space and time to insidious soft errors.
HLDVT
Kenneth M. Zick, John P. Hayes
2008 A* conf
On the role of timing masking in reliable logic circuit design.
DAC
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
2008 J jnl
Optimal synthesis of linear reversible circuits.
Quantum Inf. Comput.
Ketan N. Patel, Igor L. Markov, John P. Hayes
2008 B conf
Optimizing router locations for minimum-energy wireless networks.
LCN
Sungsoon Cho, John P. Hayes
2008 J jnl
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits.
ACM Trans. Design Autom. Electr. Syst.
Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes
2007 J jnl
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS.
IEEE J. Solid State Circuits
Jia-Yi Chen, Michael P. Flynn, John P. Hayes
2007 Misc conf
An Analysis Framework for Transient-Error Tolerance.
VTS
John P. Hayes, Ilia Polian, Bernd Becker
2007 J jnl
Checking Equivalence of Quantum Circuits and States.
CoRR
George F. Viamontes, Igor L. Markov, John P. Hayes
2007 A conf
Checking equivalence of quantum circuits and states.
ICCAD
George F. Viamontes, Igor L. Markov, John P. Hayes
2007 A conf
Enhancing design robustness with reliability-aware resynthesis and logic simulation.
ICCAD
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes
2007 — conf
Monitoring Transient Errors in Sequential Circuits.
ATS
Ramashis Das, John P. Hayes
2007 B conf
Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks.
LCN
Sungsoon Cho, John P. Hayes
2007 J jnl
Tracking Uncertainty with Probabilistic Logic Circuit Testing.
IEEE Des. Test Comput.
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
2006 — conf
A Fully Integrated Auto-Calibrated SuperRegenerative Receiver.
ISSCC
Jia-Yi Chen, Michael P. Flynn, John P. Hayes
2006 J jnl
Data structures and algorithms for simplifying reversible circuits.
ACM J. Emerg. Technol. Comput. Syst.
Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel
2006 J jnl
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Feng Gao, John P. Hayes
2006 J jnl
Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction.
J. Low Power Electron.
Feng Gao, John P. Hayes
2006 J jnl
High-level delay test generation for modular circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Joonhwan Yi, John P. Hayes
2006 B conf
On-Chip Test Generation Using Linear Subspaces.
ETS
Ramashis Das, Igor L. Markov, John P. Hayes
2005 — conf
A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS.
CICC
Jia-Yi Chen, Michael P. Flynn, John P. Hayes
2005 — conf
A Family of Logical Fault Models for Reversible Circuits.
Asian Test Symposium
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes
2005 A conf
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices.
DATE
Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes
2005 — conf
An Online Control Framework for Designing Self-Optimizing Computing Systems: Application to Power Management.
Self-star Properties in Complex Information Systems
Nagarajan Kandasamy, Sherif Abdelwahed, Gregory C. Sharp, John P. Hayes
2005 J jnl
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amit Chowdhary, John P. Hayes
2005 J jnl
Dependable communication synthesis for distributed embedded systems.
Reliab. Eng. Syst. Saf.
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
2005 — conf
Faults and Tests in Quantum Circuits.
Asian Test Symposium
John P. Hayes
2005 J jnl
Graph-based simulation of quantum computation in the density matrix representation.
Quantum Inf. Comput.
George F. Viamontes, Igor L. Markov, John P. Hayes
2005 B conf
Impact of mobility on connection in ad hoc networks.
WCNC
Sungsoon Cho, John P. Hayes
2005 J jnl
Is quantum search practical?
Comput. Sci. Eng.
George F. Viamontes, Igor L. Markov, John P. Hayes
2005 B conf
Logic circuit testing for transient faults.
ETS
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
2005 J jnl
The Coupling Model for Function and Delay Faults.
J. Electron. Test.
Joonhwan Yi, John P. Hayes
2005 J jnl
Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis.
IEEE Trans. Parallel Distributed Syst.
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
2005 A* conf
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages.
DAC
Feng Gao, John P. Hayes
2005 A conf
Transient fault characterization in dynamic noisy environments.
ITC
Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
2004 A conf
Discovering 1-FT Routes in Mobile Ad Hoc Networks.
DSN
Rajesh Venkatasubramanian, John P. Hayes
2004 A conf
Exact and heuristic approaches to input vector control for leakage power reduction.
ICCAD
Feng Gao, John P. Hayes
2004 J jnl
Fault testing for reversible circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ketan N. Patel, John P. Hayes, Igor L. Markov
2004 C conf
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction.
ICCD
Feng Gao, John P. Hayes
2004 A conf
High-Performance QuIDD-Based Simulation of Quantum Circuits.
DATE
George F. Viamontes, Igor L. Markov, John P. Hayes
2004 — conf
Self-Optimization in Computer Systems via On-Line Control: Application to Power Management.
ICAC
Nagarajan Kandasamy, Sherif Abdelwahed, John P. Hayes
2004 — conf
Testing for Missing-Gate Faults in Reversible Circuits.
Asian Test Symposium
John P. Hayes, Ilia Polian, Bernd Becker
2003 B conf
Dependable Communication Synthesis for Distributed Embedded Systems.
SAFECOMP
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
2003 Misc conf
Fault Testing for Reversible Circuits.
VTS
Ketan N. Patel, John P. Hayes, Igor L. Markov
2003 — conf
Gate-level simulation of quantum circuits.
ASP-DAC
George F. Viamontes, Manoj Rajagopalan, Igor L. Markov, John P. Hayes
2003 A conf
ILP-based optimization of sequential circuits for low power.
ISLPED
Feng Gao, John P. Hayes
2003 J jnl
Improving Gate-Level Simulation of Quantum Circuits.
Quantum Inf. Process.
George F. Viamontes, Igor L. Markov, John P. Hayes
2003 C conf
Low-Cost On-Line Fault Detection Using Control Flow Assertions.
IOLTS
Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray
2003 J jnl
On the properties of the input pattern fault model.
ACM Trans. Design Autom. Electr. Syst.
Ronald D. Blanton, John P. Hayes
2003 J jnl
On-Line Monitor Design of Finite-State Machines.
J. Electron. Test.
Feng Gao, John P. Hayes
2003 J jnl
Synthesis of reversible logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
2003 A* conf
Tutorial: basic concepts in quantum circuits.
DAC
John P. Hayes
2002 A conf
Fault-Tolerant Quantum Computers.
IPDPS
John P. Hayes
2002 J jnl
General technology mapping for field-programmable gate arrays based on lookup tables.
ACM Trans. Design Autom. Electr. Syst.
Amit Chowdhary, John P. Hayes
2002 J jnl
Guest Editorial.
J. Electron. Test.
Dimitris Nikolos, John P. Hayes, Michael Nicolaidis, Cecilia Metra
2002 — conf
On-Line Monitor Design of Finite-State Machines.
IOLTW
Feng Gao, John P. Hayes
2002 — conf
Reversible Logic Circuit Synthesis.
IWLS
Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
2002 A conf
Reversible logic circuit synthesis.
ICCAD
Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
2002 A conf
Time-Constrained Failure Diagnosis in Distributed Embedded Systems.
DSN
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
2001 — conf
A fault model for function and delay testing.
ETW
Joonhwan Yi, John P. Hayes
2001 A* conf
An Advanced Timing Characterization Method Using Mode Dependency.
DAC
Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
2001 J jnl
Delay fault testing of IP-based designs via symbolic path modeling.
IEEE Trans. Very Large Scale Integr. Syst.
HyungWon Kim, John P. Hayes
2001 J jnl
Fast and accurate timing characterization using functionalinformation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
2001 J jnl
Realization-independent ATPG for designs with unimplemented blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
HyungWon Kim, John P. Hayes
2000 J jnl
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells.
ACM Trans. Design Autom. Electr. Syst.
Avaneendra Gupta, John P. Hayes
2000 J jnl
Collection and Analysis of Microprocessor Design Errors.
IEEE Des. Test Comput.
David Van Campenhout, Trevor N. Mudge, John P. Hayes
2000 Misc conf
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits.
VTS
Hussain Al-Asaad, John P. Hayes
2000 J jnl
Logic Design Validation via Simulation and Automatic Test Pattern Generation.
J. Electron. Test.
Hussain Al-Asaad, John P. Hayes
2000 J jnl
On the design of fast, easily testable ALU's.
IEEE Trans. Very Large Scale Integr. Syst.
Ronald D. Blanton, John P. Hayes
1999 Misc conf
Delay Fault Testing of Designs with Embedded IP Cores.
VTS
HyungWon Kim, John P. Hayes
1999 A conf
Delay fault testing of IP-based designs via symbolic path modeling.
ITC
HyungWon Kim, John P. Hayes
1999 A* conf
High-Level Test Generation for Design Verification of Pipelined Microprocessors.
DAC
David Van Campenhout, Trevor N. Mudge, John P. Hayes
1999 Misc conf
Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells.
VLSI Design
Avaneendra Gupta, John P. Hayes
1999 B conf
Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems.
SRDS
Nagarajan Kandasamy, John P. Hayes, Brian T. Murray
1999 J jnl
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering.
IEEE Des. Test Comput.
Mark C. Hansen, Hakan Yalcin, John P. Hayes
1998 A conf
High-coverage ATPG for datapath circuits with unimplemented blocks.
ITC
HyungWon Kim, John P. Hayes
1998 J jnl
High-level design verification of microprocessors via error modeling.
ACM Trans. Design Autom. Electr. Syst.
David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown
1998 J jnl
Online BIST for Embedded Systems.
IEEE Des. Test Comput.
Hussain Al-Asaad, Brian T. Murray, John P. Hayes
1998 A conf
Optimal 2-D cell layout with integrated transistor folding.
ICCAD
Avaneendra Gupta, John P. Hayes
1998 J jnl
Optimal Zero-Aliasing Space Compaction of Test Responses.
IEEE Trans. Computers
Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes
1998 J jnl
Scalable Test Generators for High-Speed Datapath Circuits.
J. Electron. Test.
Hussain Al-Asaad, John P. Hayes, Brian T. Murray
1998 J jnl
Zero-aliasing space compaction of test responses using multiple parity signatures.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, John P. Hayes
1997 Misc conf
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells.
VLSI Design
Avaneendra Gupta, John P. Hayes
1997 A* conf
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells.
DAC
Avaneendra Gupta, John P. Hayes
1997 J jnl
Connective Fault Tolerance in Multiple-Bus Systems.
IEEE Trans. Parallel Distributed Syst.
Hung-Kuei Ku, John P. Hayes
1997 J jnl
Event propagation conditions in circuit delay computation.
ACM Trans. Design Autom. Electr. Syst.
Hakan Yalcin, John P. Hayes
1997 A conf
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs.
FPGA
Amit Chowdhary, John P. Hayes
1997 J jnl
On the quality of accumulator-based compaction of test responses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Krishnendu Chakrabarty, John P. Hayes
1997 C conf
Properties of the Input Pattern Fault Model.
ICCD
Ronald D. Blanton, John P. Hayes
1997 J jnl
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses.
IEEE Trans. Computers
Hung-Kuei Ku, John P. Hayes
1997 J jnl
Testability Properties of Divergent Trees.
J. Electron. Test.
R. D. (Shawn) Blanton, John P. Hayes
1997 — conf
The input pattern fault model and its application.
ED&TC
Ronald D. Blanton, John P. Hayes
1996 A conf
An approximate timing analysis method for datapath circuits.
ICCAD
Hakan Yalcin, John P. Hayes, Karem A. Sakallah
1996 J jnl
Balance testing and balance-testable design of logic circuits.
J. Electron. Test.
Krishnendu Chakrabarty, John P. Hayes
1996 Misc conf
Design of a fast, easily testable ALU.
VTS
R. D. (Shawn) Blanton, John P. Hayes
1996 J jnl
Node fault tolerance in graphs.
Networks
Frank Harary, John P. Hayes
1996 J jnl
Optimally edge fault-tolerant trees.
Networks
Hung-Kuei Ku, John P. Hayes
1996 J jnl
Test response compaction using multiplexed parity trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Krishnendu Chakrabarty, John P. Hayes
1996 J jnl
Testability of Convergent Tree Circuits.
IEEE Trans. Computers
Ronald D. Blanton, John P. Hayes
1996 J jnl
Testing ICs: Getting to the Core of the Problem.
Computer
Brian T. Murray, John P. Hayes
1996 A conf
Width minimization of two-dimensional CMOS cells using integer programming.
ICCAD
Avaneendra Gupta, John P. Hayes
1996 — conf
XPRESS: A Cell Layout Generator with Integrated Transistor Folding.
ED&TC
Avaneendra Gupta, Siang-Chun The, John P. Hayes
1995 J jnl
Cumulative balance testing of logic circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, John P. Hayes
1995 A conf
Design verification via simulation and automatic test pattern generation.
ICCAD
Hussain Al-Asaad, John P. Hayes
1995 A conf
Hierarchical timing analysis using conditional delays.
ICCAD
Hakan Yalcin, John P. Hayes
1995 A conf
High-Level Test Generation Using Symbolic Scheduling.
ITC
Mark C. Hansen, John P. Hayes
1995 Misc conf
High-level test generation using physically-induced faults.
VTS
Mark C. Hansen, John P. Hayes
1995 A conf
Optimal Space Compaction of Test Responses.
ITC
Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes
1995 A conf
Technology mapping for field-programmable gate arrays using integer programming.
ICCAD
Amit Chowdhary, John P. Hayes
1994 — conf
Connectivity and Fault Tolerance of Multiple-Bus Systems.
FTCS
Hung-Kuei Ku, John P. Hayes
1994 A* conf
DFBT: A Design-for-Testability Method Based on Balance Testing.
DAC
Krishnendu Chakrabarty, John P. Hayes
1994 A conf
Efficient Test-Response Compression for Multiple-Output Cicuits.
ITC
Krishnendu Chakrabarty, John P. Hayes
1994 J jnl
Optimal Testing and Design of Adders.
VLSI Design
Michael J. Batek, John P. Hayes
1994 — conf
Structural fault tolerance in VLSI-based systems.
Great Lakes Symposium on VLSI
Hung-Kuei Ku, John P. Hayes
1993 Misc conf
Aliasing-free error detection (ALFRED).
VTS
Krishnendu Chakrabarty, John P. Hayes
1993 — conf
Balance Testing of Logic Circuits.
FTCS
Krishnendu Chakrabarty, John P. Hayes
1993 J jnl
Edge fault tolerance in graphs.
Networks
Frank Harary, John P. Hayes
1993 — conf
Efficient Testing of Tree Circuits.
FTCS
Ronald D. Blanton, John P. Hayes
1993 J jnl
Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories.
IEEE Des. Test Comput.
Pinaki Mazumder, John P. Hayes
1993 J jnl
Reducing Inerference Among Vector Accesses in Interleaved Memories.
IEEE Trans. Computers
Ram Raghavan, John P. Hayes
1992 J jnl
A Fault-Tolerant Communication Scheme for Hypercube Computers.
IEEE Trans. Computers
Tze Chiang Lee, John P. Hayes
1992 J jnl
Accuracy of magnitude-class calculations in switch-level modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Eduard Cerny, John P. Hayes, Nicholas C. Rumin
1992 J jnl
Design of Gracefully Degradable Hypercube-Connected Systems.
J. Parallel Distributed Comput.
Tze Chiang Lee, John P. Hayes
1992 J jnl
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors.
IEEE Trans. Computers
Shantanu Dutt, John P. Hayes
1992 A* conf
Test-Set Preserving Logic Transformations.
DAC
Michael J. Batek, John P. Hayes
1991 J jnl
Designing Fault-Tolerant System Using Automorphisms.
J. Parallel Distributed Comput.
Shantanu Dutt, John P. Hayes
1991 A* conf
Exact Width and Height Minimization of CMOS Cells.
DAC
Robert L. Maziasz, John P. Hayes
1991 — conf
Scalar-Vector Memory Interference in Vector Computers.
ICPP (1)
Ram Raghavan, John P. Hayes
1991 — conf
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors.
FTCS
Shantanu Dutt, John P. Hayes
1991 J jnl
Subcube Allocation in Hypercube Computers.
IEEE Trans. Computers
Shantanu Dutt, John P. Hayes
1991 A conf
Test Propagation Through Modules and Circuits.
ITC
Brian T. Murray, John P. Hayes
1990 J jnl
A hierarchical test generation methodology for digital circuits.
J. Electron. Test.
Debashis Bhattacharya, John P. Hayes
1990 J jnl
Designing for high-level test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Debashis Bhattacharya, John P. Hayes
1990 J jnl
Hierarchical test generation using precomputed tests for modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Brian T. Murray, John P. Hayes
1990 J jnl
Layout optimization of static CMOS functional cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert L. Maziasz, John P. Hayes
1990 J jnl
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures.
IEEE Trans. Computers
Shantanu Dutt, John P. Hayes
1990 A conf
On randomly interleaved memories.
SC
Ram Raghavan, John P. Hayes
1989 — conf
An automorphic approach to the design of fault-tolerant multiprocessors.
FTCS
Shantanu Dutt, John P. Hayes
1989 J jnl
High-Level Test Generation for VLSI.
Computer
Debashis Bhattacharya, Brian T. Murray, John P. Hayes
1989 J jnl
Hypercube supercomputers.
Proc. IEEE
John P. Hayes, Trevor N. Mudge
1989 C conf
Magnitude classes in switch-level modeling.
ICCD
Eduard Cerny, John P. Hayes, Nicholas C. Rumin
1988 J jnl
A normalized-area measure for VLSI layouts.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Musaravakkam S. Krishnan, John P. Hayes
1988 — conf
Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures.
FTCS
Shantanu Dutt, John P. Hayes
1988 J jnl
Fault Recovery in Distributed Processing Loop Networks.
Comput. Networks
Raif M. Yanney, John P. Hayes
1988 A conf
Hierarchical Test Generation Using Precomputed Tests for Modules.
ITC
Brian T. Murray, John P. Hayes
1988 J jnl
Implementation of VLSI self-testing by regularization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Y. You, John P. Hayes
1988 A conf
Logic simulation on vector processors.
ICCAD
Ram Raghavan, John P. Hayes, William R. Martin
1988 — conf
On allocating subcubes in a hypercube multiprocessor.
C³P
Shantanu Dutt, John P. Hayes
1988 — conf
Routing and broadcasting in faulty hypercube computers.
C³P
Tze Chiang Lee, John P. Hayes
1987 J jnl
An Introduction to Switch-Level Modeling.
IEEE Des. Test
John P. Hayes
1987 A* conf
Layout Optimization of CMOS Functional Cells.
DAC
R. L. Maiasz, John P. Hayes
1987 J jnl
Multiple Bus Architectures.
Computer
Trevor N. Mudge, John P. Hayes, Donald C. Winsor
1986 J jnl
A Microprocessor-based Hypercube Supercomputer.
IEEE Micro
John P. Hayes, Trevor N. Mudge, Quentin F. Stout, Stephen Colley, John Palmer
1986 J jnl
An Array Layout Methodology for VLlSI Circuits.
IEEE Trans. Computers
Musaravakkam S. Krishnan, John P. Hayes
1986 J jnl
Analysis of Multiple-Bus Interconnection Networks.
J. Parallel Distributed Comput.
Trevor N. Mudge, John P. Hayes, Gregory D. Buzzard, Donald C. Winsor
1986 B conf
Architecture of a Hypercube Supercomputer.
ICPP
John P. Hayes, Trevor N. Mudge, Quentin F. Stout
1986 J jnl
Digital Simulation with Multiple Logic Values.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
John P. Hayes
1986 J jnl
Distributed Recovery in Fault-Tolerant Multiprocessor Networks.
IEEE Trans. Computers
Raif M. Yanney, John P. Hayes
1986 J jnl
Fault-tolerance and performance analysis of beta-networks.
Parallel Comput.
John Paul Shen, John P. Hayes, Luigi Ciminiera, Angelo Serra
1986 J jnl
Pseudo-Boolean Logic Circuits.
IEEE Trans. Computers
John P. Hayes
1986 J jnl
Uncertainty, Energy, and Multiple-Valued Logics.
IEEE Trans. Computers
John P. Hayes
1984 A* conf
An experimental MOS fault simulation program CSASIM.
DAC
Masato Kawai, John P. Hayes
1984 A conf
Distributed Recovery in Fault-Tolerant Multiprocessor Networks.
ICDCS
Raif M. Yanney, John P. Hayes
1984 J jnl
Fault Modeling for Digital MOS Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
John P. Hayes
1984 J jnl
Fault-Tolerance of Dynamic-Full-Access Interconnection Networks.
IEEE Trans. Computers
John Paul Shen, John P. Hayes
1982 A* conf
A fault simulation methodology for VLSI.
DAC
John P. Hayes
1981 J jnl
A Functional Approach to Testing Bit-Sliced Microprocessors.
IEEE Trans. Computers
Thirumalai Sridhar, John P. Hayes
1981 J jnl
Design of Easily Testable Bit-Sliced Systems.
IEEE Trans. Computers
Thirumalai Sridhar, John P. Hayes
1980 J jnl
Design of Totally Fault Locatable Combinational Networks.
IEEE Trans. Computers
Ayee Goundan, John P. Hayes
1980 A* conf
Fault Tolerance of a Class of Connecting Networks.
ISCA
John Paul Shen, John P. Hayes
1980 J jnl
Identification of Equivalent Faults in Logic Networks.
IEEE Trans. Computers
Ayee Goundan, John P. Hayes
1980 J jnl
Testability Considerotions in Microprocessor-Based Design.
Computer
John P. Hayes, Edward J. McCluskey
1980 J jnl
Testing Memories for Single-Cell Pattern-Sensitive Faults.
IEEE Trans. Computers
John P. Hayes
1978 J jnl
Generation of Optimal Transition Count Tests.
IEEE Trans. Computers
John P. Hayes
1978 J jnl
Path Complexity of Logic Networks.
IEEE Trans. Computers
John P. Hayes
1976 J jnl
A Graph Model for Fault-Tolerant Computing Systems.
IEEE Trans. Computers
John P. Hayes
1976 J jnl
Enumeration of Fanout-Free Boolean Functions.
J. ACM
John P. Hayes
1976 J jnl
On the Properties of Irredundant Logic Networks.
IEEE Trans. Computers
John P. Hayes
1976 A* conf
Partitioning logic circuits to maximize fault resolution.
DAC
Ayee Goundan, John P. Hayes
1976 J jnl
Transition Count Testing of Combinational Logic Circuits.
IEEE Trans. Computers
John P. Hayes
1975 J jnl
Detection of Pattern-Sensitive Faults in Random-Access Memories.
IEEE Trans. Computers
John P. Hayes
1975 J jnl
The Fanout Structure of Switching Functions.
J. ACM
John P. Hayes
1974 — conf
Minimization of Fanout in Switching Networks
SWAT
John P. Hayes
1974 J jnl
On Modifying Logic Networks to Improve Their Diagnosability.
IEEE Trans. Computers
John P. Hayes
1974 J jnl
Test Point Placement to Simplify Fault Detection.
IEEE Trans. Computers
John P. Hayes, Arthur D. Friedman
1971 J jnl
A Nand Model ror Fault Diagnosis in Combinational Logic Networks.
IEEE Trans. Computers
John P. Hayes
1971 J jnl
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests.
IEEE Trans. Computers
John P. Hayes