John Moondanos

16 papers A* 2A 2Misc 1Journal 2Unranked 9
YearRankTypeTitle / Venue / Authors
2018 — conf
A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine.
DTIS
Michael K. Tsiampas, Nestor E. Evmorfopoulos, Konstantis Daloukas, John Moondanos, Georgios I. Stamoulis
2010 A conf
Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis.
ICCAD
Nestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George I. Stamoulis, John Moondanos
2007 — conf
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability.
ATS
Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna
2006 — conf
From Error to Error: Logic Debugging in the Many-Core Era.
V&D@FLoC
John Moondanos
2006 — conf
Generation of shorter sequences for high resolution error diagnosis using sequential SAT.
ASP-DAC
Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
2005 — conf
JPEG Encoding on the Intel MXP5800: A Platform-Based Design Case Study.
ESTIMedia
Abhijit Davare, Qi Zhu, John Moondanos, Alberto L. Sangiovanni-Vincentelli
2004 J jnl
A Signal Correlation Guided Circuit-SAT Solver.
J. Univers. Comput. Sci.
Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna
2004 — conf
Preserving synchronizing sequences of sequential circuits after retiming.
ASP-DAC
Maher N. Mneimneh, Karem A. Sakallah, John Moondanos
2003 A* conf
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
DAC
Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
2002 — conf
TRANS: efficient sequential verification of loop-free circuits.
HLDVT
Zurab Khasidashvili, John Moondanos, Ziyad Hanna
2001 — conf
An enhanced cut-points algorithm in formal equivalence verification.
HLDVT
Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna
2001 A* conf
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.
CAV
John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss
1997 J jnl
Automatic verification of implementations of large circuits against HDL specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos
1994 — conf
Abstraction of data path registers for multilevel verification of large circuits.
Great Lakes Symposium on VLSI
Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell
1994 Misc conf
Verification of Circuits Described in VHDL through Extraction of Design Intent.
VLSI Design
Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell
1992 A conf
Sequential Redundancy Identification Using Verification Techniques.
ITC
John Moondanos, Jacob A. Abraham