John Lillis - RankMe

38 papers A* 9A 5Misc 1Journal 10Unranked 11

Year	Rank	Type	Title / Venue / Authors
2017	J	`jnl`	Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation. IEEE Trans. Very Large Scale Integr. Syst. Marco Rabozzi, Gianluca Carlo Durelli, Antonio Miele, John Lillis, Marco Domenico Santambrogio
2014	Misc	`conf`	Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming. FCCM Marco Rabozzi, John Lillis, Marco D. Santambrogio
2008	J	`jnl`	A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hosung Kim, John Lillis
2008	—	`conf`	A framework for layout-level logic restructuring. ISPD Hosung (Leo) Kim, John Lillis
2008	—	`ch.`	Generalized Buffer Insertion. Handbook of Algorithms for Physical Design Automation Milos Hrkic, John Lillis
2007	—	`conf`	Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. ASP-DAC Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis
2007	J	`jnl`	RBI: Simultaneous Placement and Routing Optimization Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Devang Jariwala, John Lillis
2007	—	`conf`	Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. ISPD Salim Chowdhury, John Lillis
2006	J	`jnl`	An Approach to Placement-Coupled Logic Replication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Milos Hrkic, John Lillis, Giancarlo Beraudo
2006	—	`conf`	Techniques for improved placement-coupled logic replication. ACM Great Lakes Symposium on VLSI Hosung (Leo) Kim, John Lillis, Milos Hrkic
2006	A	`conf`	Trunk decomposition based global routing optimization. ICCAD Devang Jariwala, John Lillis
2005	—	`conf`	A study of tighter lower bounds in LP relaxation based placement. ACM Great Lakes Symposium on VLSI Qingzhou (Ben) Wang, Devang Jariwala, John Lillis
2005	—	`conf`	An LP-based methodology for improved timing-driven placement. ASP-DAC Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal
2004	A*	`conf`	An approach to placement-coupled logic replication. DAC Milos Hrkic, John Lillis, Giancarlo Beraudo
2004	A	`conf`	On interactions between routing and detailed placement. ICCAD Devang Jariwala, John Lillis
2003	J	`jnl`	Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Milos Hrkic, John Lillis
2003	A*	`conf`	Timing optimization of FPGA placements by logic replication. DAC Giancarlo Beraudo, John Lillis
2002	J	`jnl`	A fast algorithm for context-aware buffer insertion. ACM Trans. Design Autom. Electr. Syst. Ashok Jagannathan, Sung-Woo Hur, John Lillis
2002	—	`conf`	Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. ISPD Milos Hrkic, John Lillis
2002	—	`ed.`	Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002 Timing Issues in the Specification and Synthesis of Digital Systems David P. LaPotin, Charles J. Alpert, John Lillis
2002	J	`jnl`	Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. VLSI Design Sung-Woo Hur, John Lillis
2002	A*	`conf`	S-Tree: a technique for buffered routing tree synthesis. DAC Milos Hrkic, John Lillis
2001	—	`conf`	Buffered Steiner trees for difficult instances. ISPD Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
2000	A*	`conf`	A fast algorithm for context-aware buffer insertion. DAC Ashok Jagannathan, Sung-Woo Hur, John Lillis
2000	A	`conf`	MONGREL: Hybrid Techniques for Standard Cell Placement. ICCAD Sung-Woo Hur, John Lillis
2000	J	`jnl`	Timing-driven maze routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sung-Woo Hur, Ashok Jagannathan, John Lillis
1999	A*	`conf`	Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. DAC Sung-Woo Hur, John Lillis
1999	—	`conf`	Timing driven maze routing. ISPD Sung-Woo Hur, Ashok Jagannathan, John Lillis
1999	J	`jnl`	Timing optimization for multisource nets: characterization andoptimal repeater insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. John Lillis, Chung-Kuan Cheng
1998	A*	`conf`	Table-Lookup Methods for Improved Performance-Driven Routing. DAC John Lillis, Premal Buch
1997	—	`conf`	A new layout-driven timing model for incremental layout optimization. ASP-DAC Fang-Jou Liu, John Lillis, Chung-Kuan Cheng
1997	A*	`conf`	Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. DAC John Lillis, Chung-Kuan Cheng
1996	A*	`conf`	New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. DAC John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho
1996	A*	`conf`	New Spectral Linear Placement and Clustering Approach. DAC Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng
1996	J	`jnl`	Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid State Circuits John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
1996	—	`conf`	Simultaneous Routing and Buffer Insertion for High Performance Interconnect. Great Lakes Symposium on VLSI John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
1995	A	`conf`	Linear decomposition algorithm for VLSI design applications. ICCAD Jianmin Li, John Lillis, Chung-Kuan Cheng
1995	A	`conf`	Optimal wire sizing and buffer insertion for low power and a generalized delay model. ICCAD John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin