John Keane

30 papers A* 1A 4C 1Journal 16Unranked 8
YearRankTypeTitle / Venue / Authors
2017 J jnl
5.6 Mb/mm
IEEE J. Solid State Circuits
Jaydeep P. Kulkarni, John Keane, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
2016 — conf
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.
ISSCC
John Keane, Jaydeep P. Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
2016 J jnl
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry.
IEEE J. Solid State Circuits
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang
2015 — conf
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology.
ISSCC
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang
2015 — conf
A 0.094um
VLSIC
Kyung-Hoae Koo, Liqiong Wei, John Keane, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang
2014 — conf
A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage.
CICC
Won Ho Choi, Saroj Satapathy, John Keane, Chris H. Kim
2014 J jnl
Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design.
IEEE Micro
Xiaofei Wang, John Keane, Tony Tae-Hyoung Kim, Pulkit Jain, Qianying Tang, Chris H. Kim
2013 J jnl
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.
IEEE J. Solid State Circuits
Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Mesut Meterelliyoz, John Keane, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr
2012 — conf
An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs.
ESSDERC
Pulkit Jain, John Keane, Chris H. Kim
2012 J jnl
Process and Reliability Sensors for Nanoscale CMOS.
IEEE Des. Test Comput.
John Keane, Chris H. Kim, Qunzeng Liu, Sachin S. Sapatnekar
2011 J jnl
An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization.
IEEE J. Solid State Circuits
John Keane, Wei Zhang, Chris H. Kim
2011 J jnl
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization.
IEEE Trans. Very Large Scale Integr. Syst.
John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim
2010 J jnl
An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB.
IEEE J. Solid State Circuits
John Keane, Xiaofei Wang, Devin Persaud, Chris H. Kim
2010 J jnl
An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation.
IEEE Trans. Very Large Scale Integr. Syst.
John Keane, Tony Tae-Hyoung Kim, Chris H. Kim
2010 J jnl
On-chip reliability monitors for measuring circuit degradation.
Microelectron. Reliab.
John Keane, Tony Tae-Hyoung Kim, Xiaofei Wang, Chris H. Kim
2009 J jnl
Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity.
IEEE Trans. Very Large Scale Integr. Syst.
Jie Gu, John Keane, Chris H. Kim
2009 J jnl
Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance.
IEEE Trans. Very Large Scale Integr. Syst.
Jie Gu, Hanyong Eom, John Keane, Chris H. Kim
2008 J jnl
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing.
IEEE J. Solid State Circuits
Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim
2008 A conf
A multi-story power delivery technique for 3D integrated circuits.
ISLPED
Pulkit Jain, Tony Tae-Hyoung Kim, John Keane, Chris H. Kim
2008 — conf
An array-based test circuit for fully automated gate dielectric breakdown characterization.
CICC
John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim
2008 C conf
Circuit techniques for ultra-low power subthreshold SRAMs.
ISCAS
Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim
2008 J jnl
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
2008 J jnl
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property.
IEEE Trans. Very Large Scale Integr. Syst.
Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim
2007 — conf
A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme.
ISSCC
Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim
2007 A conf
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation.
ISLPED
John Keane, Tony Tae-Hyoung Kim, Chris H. Kim
2007 J jnl
Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design.
IEEE Trans. Very Large Scale Integr. Syst.
Tony Tae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim
2006 A conf
Modeling and analysis of leakage induced damping effect in low voltage LSIs.
ISLPED
Jie Gu, John Keane, Chris H. Kim
2006 A* conf
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.
DAC
John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
2006 A conf
Utilizing reverse short channel effect for optimal subthreshold circuit design.
ISLPED
Tony Tae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim
2006 — conf
Width Quantization Aware FinFET Circuit Design.
CICC
Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim