John Barth - RankMe

12 papers A 1Journal 5Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A 38Mb/mm ISSCC Harold Pilo, John Barth, Kapil Dev Dwivedi, Peter Lee, Vikram Kumar, Prasanna Nalawar, Yogeshbhai Patel, Shailendra Sharad, Shakti Singh
2012	—	`conf`	Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver
2012	—	`conf`	Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. ICICDT Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer
2011	J	`jnl`	A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. IEEE J. Solid State Circuits John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao
2010	—	`conf`	A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. ISSCC John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao
2009	J	`jnl`	A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer
2008	J	`jnl`	A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2008	—	`conf`	An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. ESSCIRC Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata
2007	—	`conf`	A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2003	J	`jnl`	A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier
2001	A	`conf`	Embedded DRAM built in self test and methodology for test insertion. ITC Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek
1998	J	`jnl`	Processor-based built-in self-test for embedded DRAM. IEEE J. Solid State Circuits Jeffrey H. Dreibelbis, John Barth, Howard L. Kalter, Rex Kho