John Bainbridge

11 papers Journal 6Unranked 5

Year	Rank	Type	Title / Venue / Authors
2011	J	`jnl`	SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. ACM J. Emerg. Technol. Comput. Syst. Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge
2008	—	`conf`	An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. NOCS Luis A. Plana, John Bainbridge, Steve B. Furber, Sean Salisbury, Yebin Shi, Jian Wu
2007	—	`conf`	Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. ASYNC Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley
2005	—	`conf`	Future Trends in SoC Interconnect. SoC Steve B. Furber, John Bainbridge
2005	J	`jnl`	Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. Very Large Scale Integr. Syst. Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
2004	—	`conf`	Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium Aristides Efthymiou, John Bainbridge, Douglas A. Edwards
2004	J	`jnl`	Sparse distributed memory using Neural Networks Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple
2002	J	`jnl`	Chain: A Delay-Insensitive Chip Area Interconnect. IEEE Micro John Bainbridge, Stephen B. Furber
1994	J	`jnl`	Defining Testability Metrics Axiomatically. Softw. Test. Verification Reliab. John Bainbridge
1992	J	`jnl`	A Heuristic Method for Generating Large Random Expressions. Inf. Process. Lett. John Bainbridge
1990	—	`conf`	Obtaining Structural Metrics of Z Specifications for Systems Development. Z User Workshop John Bainbridge, Robin W. Whitty, John Wordsworth