John A. Nestor

25 papers A* 4A 1B 3C 1Journal 6Unranked 10

Year	Rank	Type	Title / Venue / Authors
2021	—	`conf`	Experiences with Remote Teaching an Embedded Systems Course. ACM Great Lakes Symposium on VLSI John A. Nestor
2017	—	`conf`	From microelectronics to making: Incorporating microelectronics in a first-year engineering course. MSE John A. Nestor
2011	—	`conf`	An undergraduate embedded systems project. MSE John F. Greco, John A. Nestor
2011	—	`conf`	HDL coding guidelines for student projects. MSE John A. Nestor
2010	B	`conf`	VCache: visualization applet for processor caches. ITiCSE Berkin Ilbeyi, John A. Nestor
2009	—	`conf`	An FPGA-based wireless network capstone project. MSE John A. Nestor, Chris Nadovich
2008	J	`jnl`	Experience With the CADAPPLETS Project. IEEE Trans. Educ. John A. Nestor
2007	—	`conf`	Experience with the CADAPPLETS Project. MSE John A. Nestor
2007	B	`conf`	L4: An FPGA-Based Accelerator for Detailed Maze Routing. FPL John A. Nestor, Jeremy Lavine
2005	J	`jnl`	L3: An FPGA-based multilayer maze routing accelerator. Microprocess. Microsystems John A. Nestor
2005	—	`conf`	Teaching Computer Organization with HDLs: An Incremental Approach. MSE John A. Nestor
2003	B	`conf`	FPGA Implementation of a Maze Routing Accelerator. FPL John A. Nestor
2003	—	`conf`	Integrating Digital, Analog, and Mixed-Signal Design in an Undergraduate ECE Curriculum. MSE John A. Nestor, David A. Rich
2002	—	`conf`	A new look at hardware maze routing. ACM Great Lakes Symposium on VLSI John A. Nestor
2001	—	`conf`	Web-Based Visualization Tools for Teaching VLSI CAD Algorithms. MSE John A. Nestor
1993	J	`jnl`	SALSA: a new approach to scheduling with timing constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. John A. Nestor, Ganesh Krishnamoorthy
1993	C	`conf`	SALSE II: A Fast Transformational Scheduler for High-level Synthesis. ISCAS Michael R. Rhinehart, John A. Nestor
1993	J	`jnl`	Visual register-transfer description of VLSI microarchitectures. IEEE Trans. Very Large Scale Integr. Syst. John A. Nestor
1992	A*	`conf`	Data Path Allocation using an Extended Binding Model. DAC Ganesh Krishnamoorthy, John A. Nestor
1990	A	`conf`	SALSA: A New Approach to Scheduling with Timing Constraints. ICCAD John A. Nestor, Ganesh Krishnamoorthy
1989	A*	`conf`	MIES: a microarchitecture design tool. MICRO John A. Nestor, Bassel Soudan, Zubair Mayet
1988	A*	`conf`	The System Architect's Workbench. DAC Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn
1984	J	`jnl`	DIF: A framework for VLSI multi-level representation. Integr. David P. LaPotin, Sani R. Nassif, Jayanth V. Rajan, Michael L. Bushnell, John A. Nestor
1983	J	`jnl`	Defining and Implementing a Multilevel Design Representation with Simulation Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Donald E. Thomas, John A. Nestor
1982	A*	`conf`	Defining and implementing a multilevel design representation with simulation applications. DAC John A. Nestor, Donald E. Thomas