| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2025 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2025 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2025 | C | conf |
ISCAS
|
| 2024 | J | jnl |
CoRR
|
| 2024 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2024 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2022 | J | jnl |
Sensors
|
| 2022 | — | conf |
ICECS 2022
|
| 2022 | — | conf |
ICECS 2022
|
| 2019 | C | conf |
ISCAS
|
| 2019 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2018 | C | conf |
ISCAS
|
| 2017 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2012 | — | conf |
ESSCIRC
|
| 2008 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2008 | J | jnl |
An Unconstrained Architecture for Systematic Design of Higher Order SigmaDelta Force-Feedback Loops.
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2007 | C | conf |
ISCAS
|
| 2005 | — | conf |
ICECS
|
| 2004 | — | conf |
ISCAS (1)
|
| 2003 | J | jnl |
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2002 | — | conf |
ISCAS (3)
|
| 2001 | J | jnl |
Signal Process.
|
| 2000 | J | jnl |
IEEE Trans. Signal Process.
|
| 1999 | — | conf |
ICECS
|
| 1999 | — | conf |
ISSPA
|