Joel S. Emer - RankMe

183 papers A* 63A 10B 18C 3Misc 3Journal 60Unranked 22

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Fast and Fusiest: An Optimal Fusion-Aware Mapper for Accelerator Modeling and Evaluation. CoRR Tanner Andrulis, Michael Gilbert, Vivienne Sze, Joel S. Emer
2026	—	`conf`	Insum: Sparse GPU Kernels Simplified and Optimized with Indirect Einsums. ASPLOS (2) Jaeyeon Won, Willow Ahrens, Saman P. Amarasinghe, Joel S. Emer
2026	J	`jnl`	Onyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications. IEEE J. Solid State Circuits Kalhan Koul, Olivia Hsu, Yuchen Mei, Sai Gautham Ravipati, Maxwell Strange, Jackson Melchert, Alex Carsello, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Zhouhua Xie, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
2026	J	`jnl`	The Turbo-Charged Mapper: Fast and Optimal Mapping for Accelerator Modeling and Evaluation. CoRR Michael Gilbert, Tanner Andrulis, Vivienne Sze, Joel S. Emer
2025	J	`jnl`	CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches. IEEE Des. Test Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel S. Emer, Mengjia Yan
2025	J	`jnl`	Derek Chiou. IEEE Micro Doug Burger, Paul Chow, Joel S. Emer, Mark D. Hill, James C. Hoe, Masato Motomura
2025	J	`jnl`	From TeAAL to FuseMax: Separation of Concerns for Attention Accelerator Design. IEEE Micro Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Xinrui Wu, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher
2025	—	`conf`	Hopps: Leveraging Sparsity to Accelerate Automata Processing. ASPLOS (3) Xingran Du, Joel S. Emer, Daniel Sánchez
2025	J	`jnl`	Insum: Sparse GPU Kernels Simplified and Optimized with Indirect Einsums. CoRR Jaeyeon Won, Willow Ahrens, Joel S. Emer, Saman P. Amarasinghe
2025	A*	`conf`	Quartz: A Reconfigurable, Distributed-Memory Accelerator for Sparse Applications. MICRO Courtney Golden, Axel Feldmann, Joel S. Emer, Daniel Sánchez
2025	—	`conf`	SquareLoop: Explore Optimal Authentication Block Strategy for ML. HASP@MICRO Jan Strzeszynski, Jianming Tong, Kyungmi Lee, Nathan Xiong, Angshuman Parashar, Joel S. Emer, Tushar Krishna, Mengjia Yan
2025	J	`jnl`	The Continuous Tensor Abstraction: Where Indices Are Real. Proc. ACM Program. Lang. Jaeyeon Won, Willow Ahrens, Teodoro Fields Collin, Joel S. Emer, Saman P. Amarasinghe
2025	J	`jnl`	Understanding Error Propagation in Deep-Learning Neural Networks' Accelerators and Applications. IEEE Des. Test Guanpeng Li, Siva Kumar Sastry Hari, Michael B. Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel S. Emer, Stephen W. Keckler
2024	B	`conf`	Architecture-Level Modeling of Photonic Deep Neural Network Accelerators. ISPASS Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M. Suriyakumar, Joel S. Emer, Vivienne Sze
2024	J	`jnl`	Architecture-Level Modeling of Photonic Deep Neural Network Accelerators. CoRR Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M. Suriyakumar, Joel S. Emer, Vivienne Sze
2024	A*	`conf`	Azul: An Accelerator for Sparse Iterative Solvers Leveraging Distributed On-Chip Memory. MICRO Axel Feldmann, Courtney Golden, Yifan Yang, Joel S. Emer, Daniel Sánchez
2024	B	`conf`	CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool. ISPASS Tanner Andrulis, Joel S. Emer, Vivienne Sze
2024	J	`jnl`	CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool. CoRR Tanner Andrulis, Joel S. Emer, Vivienne Sze
2024	A*	`conf`	DelayAVF: Calculating Architectural Vulnerability Factors for Delay Faults. MICRO Peter W. Deutsch, Vincent Quentin Ulitzsch, Sudhanva Gurumurthi, Vilas Sridharan, Joel S. Emer, Mengjia Yan
2024	A*	`conf`	FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design. MICRO Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher
2024	J	`jnl`	FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design. CoRR Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher
2024	J	`jnl`	LoopTree: Exploring the Fused-Layer Dataflow Accelerator Design Space. IEEE Trans. Circuits Syst. Artif. Intell. Michael Gilbert, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
2024	J	`jnl`	LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space. CoRR Michael Gilbert, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
2024	A*	`conf`	Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms. ISCA Qijing Huang, Po-An Tsai, Joel S. Emer, Angshuman Parashar
2024	J	`jnl`	Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design. CoRR Tanner Andrulis, Ruicong Chen, Hae-Seung Lee, Joel S. Emer, Vivienne Sze
2024	—	`conf`	Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications. VLSI Technology and Circuits Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
2024	—	`conf`	Onyx: A Programmable Accelerator for Sparse Tensor Algebra. HCS Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
2024	—	`conf`	TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators (Abstract). HOPC@SPAA Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
2024	J	`jnl`	The Continuous Tensor Abstraction: Where Indices are Real. CoRR Jaeyeon Won, Willow Ahrens, Joel S. Emer, Saman P. Amarasinghe
2024	J	`jnl`	The EDGE Language: Extended General Einsums for Graph Algorithms. CoRR Toluwanimi O. Odemuyiwa, Joel S. Emer, John D. Owens
2024	A*	`conf`	Trapezoid: A Versatile Accelerator for Dense and Sparse Matrix Multiplications. ISCA Yifan Yang, Joel S. Emer, Daniel Sánchez
2023	A*	`conf`	Accelerating RTL Simulation with Hardware-Software Co-Design. MICRO Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, Joel S. Emer, Daniel Sánchez
2023	—	`conf`	Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract). HOPC@SPAA Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
2023	—	`conf`	Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. ASPLOS (3) Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
2023	A*	`conf`	HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. MICRO Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2023	J	`jnl`	HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. CoRR Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2023	A*	`conf`	ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining. HPCA Yifan Yang, Joel S. Emer, Daniel Sánchez
2023	B	`conf`	LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. ISPASS Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2023	A*	`conf`	Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes. ISCA Peter W. Deutsch, Weon Taek Na, Thomas Bourgeat, Joel S. Emer, Mengjia Yan
2023	B	`conf`	Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. DCC Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer
2023	—	`conf`	Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. HPEC Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer
2023	J	`jnl`	Penetrating Shields: A Systematic Analysis of Memory Corruption Mitigations in the Spectre Era. CoRR Weon Taek Na, Joel S. Emer, Mengjia Yan
2023	A*	`conf`	RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! ISCA Tanner Andrulis, Joel S. Emer, Vivienne Sze
2023	J	`jnl`	RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! CoRR Tanner Andrulis, Joel S. Emer, Vivienne Sze
2023	A*	`conf`	SecureLoop: Design Space Exploration of Secure DNN Accelerators. MICRO Kyungmi Lee, Mengjia Yan, Joel S. Emer, Anantha P. Chandrakasan
2023	J	`jnl`	Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing. ACM Trans. Comput. Syst. Michael Pellauer, Jason Clemons, Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Donghyuk Lee, Mike O'Connor, Anghsuman Parashar, Sean Treichler, Po-An Tsai, Stephen W. Keckler, Joel S. Emer
2023	A*	`conf`	Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. MICRO Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
2023	J	`jnl`	Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. CoRR Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
2023	A*	`conf`	TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. MICRO Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
2023	J	`jnl`	TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. CoRR Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
2023	—	`conf`	The Sparse Abstract Machine. ASPLOS (3) Olivia Hsu, Maxwell Strange, Ritvik Sharma, Jaeyeon Won, Kunle Olukotun, Joel S. Emer, Mark A. Horowitz, Fredrik Kjølstad
2023	—	`conf`	Unified Convolution Framework: A compiler-based approach to support sparse convolutions. MLSys Jaeyeon Won, Changwan Hong, Charith Mendis, Joel S. Emer, Saman P. Amarasinghe
2023	—	`conf`	WACO: Learning Workload-Aware Co-optimization of the Format and Schedule of a Sparse Tensor Program. ASPLOS (2) Jaeyeon Won, Charith Mendis, Joel S. Emer, Saman P. Amarasinghe
2022	A*	`conf`	DAGguise: mitigating memory timing side channels. ASPLOS Peter W. Deutsch, Yuheng Yang, Thomas Bourgeat, Jules Drean, Joel S. Emer, Mengjia Yan
2022	B	`conf`	Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization. ISPASS Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel S. Emer, Siddharth Joshi
2022	A*	`conf`	Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. MICRO Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2022	J	`jnl`	Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. CoRR Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2022	J	`jnl`	The Sparse Abstract Machine. CoRR Olivia Hsu, Maxwell Strange, Jaeyeon Won, Ritvik Sharma, Kunle Olukotun, Joel S. Emer, Mark Horowitz, Fredrik Kjolstad
2021	B	`conf`	Architecture-Level Energy Estimation for Heterogeneous Computing Systems. ISPASS Francis Wang, Yannan Nellie Wu, Matthew E. Woicik, Joel S. Emer, Vivienne Sze
2021	A*	`conf`	Gamma: leveraging Gustavson's algorithm to accelerate sparse matrix multiplication. ASPLOS Guowei Zhang, Nithya Attaluri, Joel S. Emer, Daniel Sánchez
2021	Misc	`conf`	Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future. WCAE Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, Abdulrahman Mahmoud, Saugata Ghose, Joel S. Emer
2021	J	`jnl`	Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
2021	A*	`conf`	SpZip: Architectural Support for Effective Data Compression In Irregular Applications. ISCA Yifan Yang, Joel S. Emer, Daniel Sánchez
2021	B	`conf`	Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. ISPASS Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
2020	J	`jnl`	A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2020	B	`conf`	An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs. ISPASS Yannan Nellie Wu, Vivienne Sze, Joel S. Emer
2020	A*	`conf`	CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches. MICRO Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel S. Emer, Mengjia Yan
2020	—	`book`	Efficient Processing of Deep Neural Networks Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer
2020	J	`jnl`	Estimating Silent Data Corruption Rates Using a Two-Level Model. CoRR Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip P. Shirvani, Paul Racunas, Joel S. Emer, Stephen W. Keckler
2020	J	`jnl`	Freely scalable and reconfigurable optical hardware for deep learning. CoRR Liane Bernstein, Alexander Sludds, Ryan Hamerly, Vivienne Sze, Joel S. Emer, Dirk R. Englund
2019	—	`conf`	A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2019	—	`conf`	A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2019	A	`conf`	Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs. ICCAD Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
2019	A*	`conf`	Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. ASPLOS Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer
2019	A*	`conf`	ExTensor: An Accelerator for Sparse Tensor Algebra. MICRO Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
2019	J	`jnl`	Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer, Vivienne Sze
2019	A	`conf`	MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
2019	A*	`conf`	Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
2019	B	`conf`	Timeloop: A Systematic Approach to DNN Accelerator Evaluation. ISPASS Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer
2018	A*	`conf`	A modular digital VLSI flow for high-productivity SoC design. DAC Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer
2018	A*	`conf`	DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors. MICRO Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer
2018	J	`jnl`	DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors. IACR Cryptol. ePrint Arch. Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer
2018	J	`jnl`	Eyeriss v2: A Flexible and High-Performance Accelerator for Emerging Deep Neural Networks. CoRR Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
2018	—	`conf`	Hardware for machine learning: Challenges and opportunities. CICC Vivienne Sze, Yu-Hsin Chen, Joel S. Emer, Amr Suleiman, Zhengdong Zhang
2018	A*	`conf`	Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism. MICRO Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel S. Emer, Daniel Sánchez
2017	J	`jnl`	(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies. ACM Trans. Reconfigurable Technol. Syst. Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Michael Adler, Joel S. Emer
2017	Misc	`conf`	A method to estimate the energy consumption of deep neural networks. ACSSC Tien-Ju Yang, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
2017	A	`conf`	Automatic Construction of Program-Optimized FPGA Memory Networks. FPGA Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer
2017	J	`jnl`	Efficient Processing of Deep Neural Networks: A Tutorial and Survey. CoRR Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer
2017	J	`jnl`	Efficient Processing of Deep Neural Networks: A Tutorial and Survey. Proc. IEEE Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer
2017	J	`jnl`	Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. IEEE J. Solid State Circuits Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze
2017	A*	`conf`	Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism. ISCA Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel S. Emer, Daniel Sánchez
2017	A*	`ed.`	Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017 MICRO Hillery C. Hunter, Jaime Moreno, Joel S. Emer, Daniel Sánchez
2017	B	`conf`	SAM: Optimizing Multithreaded Cores for Speculative Parallelism. PACT Maleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey, Joel S. Emer, Daniel Sánchez
2017	B	`conf`	SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation. ISPASS Siva Kumar Sastry Hari, Timothy Tsai, Mark Stephenson, Stephen W. Keckler, Joel S. Emer
2017	A*	`conf`	SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
2017	J	`jnl`	SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
2017	J	`jnl`	Towards Closing the Energy Gap Between HOG and CNN Features for Embedded Vision. CoRR Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
2017	C	`conf`	Towards closing the energy gap between HOG and CNN features for embedded vision (Invited paper). ISCAS Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
2017	A	`conf`	Understanding error propagation in deep learning neural network (DNN) accelerators and applications. SC Guanpeng Li, Siva Kumar Sastry Hari, Michael B. Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel S. Emer, Stephen W. Keckler
2017	J	`jnl`	Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators. IEEE Micro Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
2016	—	`conf`	14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. ISSCC Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze
2016	—	`conf`	CLARA: Circular Linked-List Auto and Self Refresh Architecture. MEMSYS Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel S. Emer, Stephen W. Keckler
2016	A*	`conf`	Data-centric execution of speculative parallel programs. MICRO Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Sánchez
2016	A*	`conf`	Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks. ISCA Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
2016	J	`jnl`	Hardware for Machine Learning: Challenges and Opportunities. CoRR Vivienne Sze, Yu-Hsin Chen, Joel S. Emer, Amr Suleiman, Zhengdong Zhang
2016	A	`conf`	LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning. FPGA Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer
2016	J	`jnl`	Unlocking Ordered Parallelism with the Swarm Architecture. IEEE Micro Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez
2015	A*	`conf`	A fast and accurate analytical technique to compute the AVF of sequential bits in a processor. MICRO Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer
2015	A*	`conf`	A scalable architecture for ordered parallelism. MICRO Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez
2015	J	`jnl`	Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer
2015	A*	`conf`	High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches. HPCA Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel S. Emer
2015	B	`conf`	Scavenger: Automating the construction of application-optimized memory hierarchies. FPL Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer
2014	J	`jnl`	Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
2014	B	`conf`	Exploiting spatial architectures for edit distance algorithms. ISPASS Jesmin Jahan Tithi, Neal Clayton Crago, Joel S. Emer
2014	Misc	`conf`	LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories. FCCM Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer
2014	B	`conf`	The LEAP FPGA operating system. FPL Kermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer
2013	—	`conf`	A Hierarchical Architectural Framework for Reconfigurable Logic Computing. IPDPS Workshops Peng Li, Angshuman Parashar, Michael Pellauer, Tao Wang, Joel S. Emer
2013	B	`conf`	Optimizing under abstraction: Using prefetching to improve FPGA performance. FPL Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer
2013	A*	`conf`	Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
2013	J	`jnl`	Using in-flight chains to build a scalable cache coherence protocol. ACM Trans. Archit. Code Optim. Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer
2012	A*	`conf`	CRUISE: cache replacement and utility-aware scheduling. ASPLOS Aamer Jaleel, Hashem Hashemi Najaf-abadi, Samantika Subramaniam, Simon C. Steely Jr., Joel S. Emer
2012	A	`conf`	Leveraging latency-insensitivity to ease multiple FPGA design. FPGA Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer
2012	A*	`conf`	Scheduling heterogeneous multi-cores through performance impact estimation (PIE). ISCA Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer
2012	J	`jnl`	The gradient-based cache partitioning algorithm. ACM Trans. Archit. Code Optim. William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon C. Steely Jr., Joel S. Emer
2012	—	`conf`	ZIP-IO: Architecture for application-specific compression of Big Data. FPT Sang Woo Jun, Kermin Fleming, Michael Adler, Joel S. Emer
2011	—	`ch.`	DEC Alpha. Encyclopedia of Parallel Computing Joel S. Emer, Tryggve Fossum
2011	A*	`conf`	HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. HPCA Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer
2011	A	`conf`	Leap scratchpads: automatic memory and cache management for reconfigurable logic. FPGA Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer
2011	A*	`conf`	PACMan: prefetch-aware cache management for high performance caching. MICRO Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer
2011	A*	`conf`	SHiP: signature-based hit predictor for high performance caching. MICRO Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer
2010	A*	`conf`	Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies. MICRO Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer
2010	C	`conf`	Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). MEMOCODE Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer
2010	A*	`conf`	High performance cache replacement using re-reference interval prediction (RRIP). ISCA Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer
2010	J	`jnl`	The Future of Architectural Simulation. IEEE Micro James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi
2009	J	`jnl`	A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2009	B	`conf`	Accelerating architecture research. ISPASS Joel S. Emer
2009	A*	`conf`	CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. HPCA Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit Riaz Sheikh, Shrirang M. Yardi
2009	J	`jnl`	Guest Editors' Introduction: Top Picks from the 2008 Computer Architecture Conferences. IEEE Micro Joel S. Emer, Dean M. Tullsen
2009	—	`ed.`	High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings HiPEAC André Seznec, Joel S. Emer, Michael F. P. O'Boyle, Margaret Martonosi, Theo Ungerer
2009	A*	`conf`	Soft connections: addressing the hardware-design modularity problem. DAC Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer
2008	A	`conf`	A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2008	B	`conf`	Adaptive insertion policies for managing shared caches. PACT Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer
2008	J	`jnl`	Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal. IEEE Comput. Archit. Lett. Arijit Biswas, Paul Racunas, Joel S. Emer, Shubhendu S. Mukherjee
2008	B	`conf`	Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2008	J	`jnl`	Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
2007	A*	`conf`	Adaptive insertion policies for high performance caching. ISCA Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
2007	A*	`conf`	Late-binding: enabling unordered load-store queues. ISCA Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler
2007	J	`jnl`	Single-Threaded vs. Multithreaded: Where Should We Focus? IEEE Micro Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag
2005	A*	`conf`	Computing Architectural Vulnerability Factors for Address-Based Structures. ISCA Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan
2005	A*	`conf`	The Soft Error Problem: An Architectural Perspective. HPCA Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt
2004	C	`conf`	Cache Scrubbing in Microprocessors: Myth or Necessity? PRDC Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt
2004	J	`jnl`	Reducing the Soft-Error Rate of a High-Performance Microprocessor. IEEE Micro Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt
2004	A*	`conf`	Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. ISCA Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt
2003	A*	`conf`	A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. MICRO Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin
2003	J	`jnl`	Measuring Architectural Vulnerability Factors. IEEE Micro Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin
2002	A*	`conf`	A comparative study of arbitration algorithms for the Alpha 21364 pipelined router. ASPLOS Shubhendu S. Mukherjee, Federico Silla, Peter J. Bannon, Joel S. Emer, Steven Lang, David Webb
2002	J	`jnl`	Asim: A Performance Model Framework. Computer Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan
2002	A*	`conf`	Loose Loops Sink Chips. HPCA Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer
2002	J	`jnl`	Performance Simulation Tools. Computer Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson
2002	A*	`conf`	Tarantula: A Vector Extension to the Alpha Architecture. ISCA Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
2000	A*	`ed.`	27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada ISCA Alan D. Berenbaum, Joel S. Emer
2000	A*	`conf`	Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. HPCA Harish Patil, Joel S. Emer
1999	A	`conf`	Reducing cache misses using hardware and software page placement. International Conference on Supercomputing Timothy Sherwood, Brad Calder, Joel S. Emer
1999	A*	`conf`	The Use of Multithreading for Exception Handling. MICRO Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi
1998	—	`conf`	A Characterization of Processor Performance in the VAX-11/780. 25 Years ISCA: Retrospectives and Reprints Joel S. Emer, Douglas W. Clark
1998	A*	`conf`	Memory Dependence Prediction Using Store Sets. ISCA George Z. Chrysos, Joel S. Emer
1998	—	`conf`	Retrospective: Characterization of Processor Performance in the VAX-11/780. 25 Years ISCA: Retrospectives and Reprints Joel S. Emer, Douglas W. Clark
1997	A*	`conf`	A Language for Describing Predictors and Its Application to Automatic Synthesis. ISCA Joel S. Emer, Nicholas C. Gloy
1997	J	`jnl`	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. ACM Trans. Comput. Syst. Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen
1997	J	`jnl`	Simultaneous multithreading: a platform for next-generation processors. IEEE Micro Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm, Dean M. Tullsen
1996	A*	`conf`	Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. ISCA Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm
1996	J	`jnl`	Incremental Versus Revolutionary Research. ACM Comput. Surv. Joel S. Emer
1996	A*	`conf`	Predictive Sequential Associative Cache. HPCA Brad Calder, Dirk Grunwald, Joel S. Emer
1995	A*	`conf`	A system level perspective on branch architecture performance. MICRO Brad Calder, Dirk Grunwald, Joel S. Emer
1995	A*	`conf`	Instruction Fetching: Coping with Code Bloat. ISCA Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer
1989	A*	`ed.`	ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989. ASPLOS Joel S. Emer, John L. Hennessy
1989	J	`jnl`	Performance Analysis of Mass Storage Service Alternatives for Distributed Systems. IEEE Trans. Software Eng. K. K. Ramakrishnan, Joel S. Emer
1988	A	`conf`	Performance Considerations for Distributed Services: A Case Study: Mass Storage. ICDCS Joel S. Emer, K. K. Ramakrishnan
1986	—	`conf`	Design analysis of a heterogeneous distributed system. ACM SIGOPS European Workshop Joel S. Emer, K. K. Ramakrishnan
1985	J	`jnl`	Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement ACM Trans. Comput. Syst. Douglas W. Clark, Joel S. Emer
1984	A*	`conf`	A Characterization of Processor Performance in the VAX-11/780. ISCA Joel S. Emer, Douglas W. Clark
1979	—	`—`	Shared Resources for Multiple Instruction Stream Pipelined Processors Joel S. Emer