Joel Grodstein

22 papers A* 1A 9C 3Misc 1Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2011 J jnl
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems.
J. Electron. Test.
Desta Tadesse, R. Iris Bahar, Joel Grodstein
2009 A conf
AutoRex: An automated post-silicon clock tuning tool.
ITC
Desta Tadesse, Joel Grodstein, R. Iris Bahar
2008 Misc conf
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation.
VTS
Desta Tadesse, R. Iris Bahar, Joel Grodstein
2007 A conf
Accurate timing analysis using SAT and pattern-dependent delay models.
DATE
Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein
2006 J jnl
Timing analysis for full-custom circuits using symbolic DC formulations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein
2005 J jnl
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein
2004 — conf
RESTA: a robust and extendable symbolic timing analysis tool.
ACM Great Lakes Symposium on VLSI
Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
2003 C conf
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor.
ICCD
Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies
2003 C conf
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current.
ICCD
Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein
2002 — conf
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU.
ACM Great Lakes Symposium on VLSI
Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton
2002 — conf
Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations.
IWLS
Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
1998 J jnl
A low-cost, 300-MHz, RISC CPU with attached media processor.
IEEE J. Solid State Circuits
Sribalan Santhanam, Allen J. Baum, David Bertucci, Mike Braganza, Kevin Broch, Todd Broch, James Burnette, Edward Chang, Kwong-Tak Chui, Dan Dobberpuhl, Paul M. Donahue, Joel Grodstein, Insung Kim, Daniel Murray, Mark H. Pearce, Amy Silveria, Dave Souydalay, Aaron Spink, Robert Stepanian, Anand Varadharajan, Vincent R. von Kaenel, Ricky Wen
1998 C conf
Static race verification for networks with reconvergent clocks.
ICCD
Joel Grodstein, Nick Rethman, Nevine Nassif
1997 J jnl
Logic decomposition during technology mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
1995 A conf
A delay model for logic synthesis of continuously-sized networks.
ICCAD
Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe
1995 A conf
Logic decomposition during technology mapping.
ICCAD
Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
1994 A conf
Optimal latch mapping and retiming within a tree.
ICCAD
Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann
1993 A conf
A simple algorithm for fanout optimization using high-performance buffer libraries.
ICCAD
K. Kodandapani, Joel Grodstein, Antun Domic, Hervé J. Touati
1991 A conf
Automatic Detection of MOS Synchronizers for Timing Verification.
ICCAD
Joel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff
1991 A* conf
Timing Verification on a 1.2M-Device Full-Custom CMOS Design.
DAC
Jengwei Pan, Larry L. Biro, Joel Grodstein, William J. Grundmann, Yao-Tsung Yen
1990 A conf
Constraint Identification for Timing Verification.
ICCAD
Joel Grodstein, Jengwei Pan, William J. Grundmann, Bruce Gieseke, Yao-Tsung Yen
1990 A conf
Race Detection for Two-Phase Systems.
ICCAD
Joel Grodstein, Jim Montanaro, Susanne Marino