Jochen A. G. Jess

57 papers A* 4A 16C 2Misc 2Journal 13Unranked 18

Year	Rank	Type	Title / Venue / Authors
2006	J	`jnl`	Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
2003	J	`jnl`	Codeübersetzung unter Zeitvorgaben für eingebettete Signalprozessoren (Performance Controlled Compilation for Embedded Signal Processors). it Inf. Technol. Jochen A. G. Jess
2003	A*	`conf`	Statistical timing for parametric yield prediction of digital integrated circuits. DAC Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
2002	—	`conf`	Parametric Yield Estimation for Deep Sub- Micron VLSI Circuits. SBCCI Jochen A. G. Jess
2001	A	`conf`	Constraint Satisfaction for Relative Location Assignment and Scheduling. ICCAD Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess
2001	A	`conf`	Constraint satisfaction for storage files with Fifos or stacks during scheduling. DATE Carlos A. Alba Pinto, Bart Mesman, Koen van Eijk, Jochen A. G. Jess
2001	—	`conf`	Phase coupled operation assignment for VLIW processors with distributed register files. ISSS Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen
2001	—	`conf`	Static resource models of instruction sets. ISSS Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess
2000	J	`jnl`	A code-motion pruning technique for global scheduling. ACM Trans. Design Autom. Electr. Syst. Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess
2000	—	`conf`	Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP Algorithms. SBCCI Carlos A. Alba Pinto, Koen van Eijk, Bart Mesman, Jochen A. G. Jess
2000	J	`jnl`	Constraint analysis for code generation: basic techniques and applications in FACTS. ACM Trans. Design Autom. Electr. Syst. Koen van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess
2000	J	`jnl`	Designing electronic engines with electronic engines: 40 years ofbootstrapping of a technology upon itself. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jochen A. G. Jess
2000	J	`jnl`	Prophid: A Platform-Based Design Method. Des. Autom. Embed. Syst. Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
2000	—	`conf`	Register Binding for Predicated Execution in DSP Applications. SBCCI Qin Zhao, C. A. J. van Eijk, Carlos A. Alba Pinto, Jochen A. G. Jess
1999	A*	`conf`	A Reordering Technique for Efficient Code Motion. DAC Luiz C. V. dos Santos, Jochen A. G. Jess
1999	J	`jnl`	Constraint analysis for DSP code generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
1999	A	`conf`	Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation. DATE Luiz C. V. dos Santos, Jochen A. G. Jess
1998	A	`conf`	A Constraint Driven Approach to Loop Pipelining and Register Binding. DATE Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
1998	A	`conf`	Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. DATE Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
1997	—	`conf`	Constraint Analysis for DSP Code Generation. ISSS Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
1997	C	`conf`	PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. ICCD Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
1997	—	`conf`	PROPHID: a data-driven multi-processor architecture for high-performance DSP. ED&TC Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
1996	—	`conf`	A Constructive Method for Exploiting Code Motion. ISSS Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess
1996	J	`jnl`	An efficient CMOS bridging fault simulator: with SPICE accuracy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chennian Di, Jochen A. G. Jess
1996	J	`jnl`	Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
1996	—	`conf`	Exploiting Functional Dependencies in Finite State Machine Verification. ED&TC C. A. J. van Eijk, Jochen A. G. Jess
1995	—	`conf`	Analysis and reduction of glitches in synchronous networks. ED&TC Jeroen A. J. Leijten, Jef L. van Meerbergen, Jochen A. G. Jess
1995	A*	`conf`	Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. DAC Adwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess
1995	—	`conf`	Efficient code generation for in-house DSP-cores. ED&TC Marino T. J. Strik, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess, Stefaan Note
1995	—	`conf`	Exact scheduling strategies based on bipartite graph matching. ED&TC Adwin H. Timmer, Jochen A. G. Jess
1995	—	`conf`	High-level synthesis scheduling and allocation using genetic algorithms. ASP-DAC Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess
1995	—	`conf`	Run-time consistency checking in discrete simulation models. ED&TC J. W. G. Fleurkens, C. A. J. van Eijk, Jochen A. G. Jess
1994	A	`conf`	Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. ICCAD Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
1994	C	`conf`	NEAT: An Object Oriented High-Level Synthesis Interface. ISCAS M. J. M. Heijiligers, H. A. Hilderink, Adwin H. Timmer, Jochen A. G. Jess
1994	—	`conf`	On Design Rule Correct Maze Routing. EDAC-ETC-EUROASIC Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess
1994	—	`conf`	Probability Analysis for CMOS Floating Gate Faults. EDAC-ETC-EUROASIC Hua Xue, Chennian Di, Jochen A. G. Jess
1994	A	`ed.`	Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994 ICCAD Jochen A. G. Jess, Richard L. Rudell
1994	A*	`conf`	Routing for Manufacturability. DAC Hua Xue, Ed P. Huijbregts, Jochen A. G. Jess
1993	Misc	`conf`	A Multiple Terminal Net Routing Algorithm Using Failure Prediction. VLSI Design Ed P. Huijbregts, Jochen A. G. Jess
1993	A	`conf`	A net-oriented method for realistic fault analysis. ICCAD Hua Xue, Chennian Di, Jochen A. G. Jess
1993	A	`conf`	Execution interval analysis under resource constraints. ICCAD Adwin H. Timmer, Jochen A. G. Jess
1993	—	`conf`	Fast Multi-Layer Critical Area Computation. DFT Hua Xue, Chennian Di, Jochen A. G. Jess
1993	J	`jnl`	General gate array routing using a k-terminal net routing algorithm with failure prediction. IEEE Trans. Very Large Scale Integr. Syst. Ed P. Huijbregts, Jochen A. G. Jess
1993	A	`conf`	On Accurate Modeling and Efficient Simulation of CMOS Opens. ITC Chennian Di, Jochen A. G. Jess
1993	Misc	`conf`	On CMOS bridge fault modeling and test pattern evaluation. VTS Chennian Di, Jochen A. G. Jess
1993	A	`conf`	Parameter Monitoring: Advantages and Pitfalls. ITC M. M. A. van Rosmalen, Keith Baker, Eric Bruls, Jochen A. G. Jess
1993	A	`ed.`	Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993 ICCAD Michael R. Lightner, Jochen A. G. Jess
1992	J	`jnl`	Foreground memory management in data path synthesis. Int. J. Circuit Theory Appl. Leon Stok, Jochen A. G. Jess
1991	A	`conf`	A Generic Method to Develop a Defect Monitoring System for IC Processes. ITC Eric Bruls, F. Camerik, H. J. Kretschman, Jochen A. G. Jess
1991	—	`ed.`	Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991 EURO-DAC Tony Ambler, Jochen A. G. Jess, Hugo De Man
1990	—	`ed.`	European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990 EURO-DAC Gordon Adshead, Jochen A. G. Jess
1990	—	`conf`	Gate sizing in MOS digital circuits with linear programming. EURO-DAC Michel R. C. M. Berkelaar, Jochen A. G. Jess
1989	A	`conf`	A layout defect-sensitivity extractor. ICCAD José Pineda de Gyvez, Jochen A. G. Jess
1989	J	`jnl`	On the design and implementation of a wafer yield editor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José Pineda de Gyvez, Jochen A. G. Jess
1989	A	`conf`	Qualification and Quantification of Process-Induced Product-Related Defects. ITC F. Camerik, P. A. J. Dirks, Jochen A. G. Jess
1988	A	`conf`	Technology mapping for standard-cell generators. ICCAD Michel R. C. M. Berkelaar, Jochen A. G. Jess
1982	J	`jnl`	A Data Structure for Parallel IEEE Trans. Computers Jochen A. G. Jess, H. G. M. Kees