Joan Figueras - RankMe

130 papers A 18B 11C 5Misc 14Journal 46Unranked 36

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Indirect and adaptive test of analogue circuits based on preselected steady-state response measures. IET Circuits Devices Syst. Álvaro Gómez-Pau, Emili Lupon, Luz Balado, Joan Figueras
2019	J	`jnl`	Postbond Test of Through-Silicon Vias With Resistive Open Defects. IEEE Trans. Very Large Scale Integr. Syst. Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras
2017	B	`conf`	Mitigating read & write errors in STT-MRAM memories under DVS. ETS Elena-Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras
2017	J	`jnl`	Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing. J. Electron. Test. Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2016	J	`jnl`	Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2016	J	`jnl`	Indirect test of M-S circuits using multiple specification band guarding. Integr. Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2016	J	`jnl`	Prebond Testing of Weak Defects in TSVs. IEEE Trans. Very Large Scale Integr. Syst. Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
2016	J	`jnl`	Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents. IEEE Trans. Very Large Scale Integr. Syst. Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
2015	—	`conf`	Analog circuits testing using digitally coded indirect measurements. DTIS Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2015	B	`conf`	Power-aware voltage tuning for STT-MRAM reliability. ETS Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
2015	A	`conf`	Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. DATE Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
2015	—	`conf`	STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations. DTIS Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Paolo Prinetto, Joan Figueras
2014	B	`conf`	M-S specification binning based on digitally coded indirect measurements. ETS Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2014	B	`conf`	Post-bond test of Through-Silicon Vias with open defects. ETS Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras
2014	C	`conf`	Pre-bond testing of weak defects in TSVs. IOLTS Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
2014	—	`conf`	Reliability estimation at block-level granularity of spin-transfer-torque MRAMs. DFT Stefano Di Carlo, Marco Indaco, Paolo Prinetto, Elena I. Vatajelu, Rosa Rodríguez-Montañés, Joan Figueras
2014	J	`jnl`	Skew violation verification in digital interconnect signals based on signal addition. IEICE Electron. Express Víctor H. Champac, Hector Villacorta, Nestor Hernandez, Joan Figueras
2014	J	`jnl`	Sram cell stability metric under transient voltage noise. Microelectron. J. Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras
2013	B	`conf`	BIST architecture to detect defects in tsvs during pre-bond testing. ETS Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
2013	J	`jnl`	Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2013	B	`conf`	M-S test based on specification validation using octrees in the measure space. ETS Álvaro Gómez-Pau, Luz Balado, Joan Figueras
2012	A	`conf`	Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation. DATE Elena I. Vatajelu, Joan Figueras
2011	J	`jnl`	Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2011	J	`jnl`	Gate Leakage Impact on Full Open Defects in Interconnect Lines. IEEE Trans. Very Large Scale Integr. Syst. Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2011	C	`conf`	New reliability mechanisms in memory design for sub-22nm technologies. IOLTS Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanausú Ramírez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang, Paul Zuber
2011	A	`conf`	Robustness analysis of 6T SRAMs in memory retention mode under PVT variations. DATE Elena I. Vatajelu, Joan Figueras
2011	C	`conf`	Statistical analysis of 6T SRAM data retention voltage under process variation. DDECS Elena-Ioana Vatajelu, Joan Figueras
2011	—	`conf`	Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric. Asian Test Symposium Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras
2011	C	`conf`	Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies. IOLTS Madalin Neagu, Liviu Miclea, Joan Figueras
2010	A	`conf`	Analog circuit test based on a digital signature. DATE Alvaro Gómez, Ricard Sanahuja, Luz Balado, Joan Figueras
2010	J	`jnl`	Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. IEEE Trans. Very Large Scale Integr. Syst. Víctor H. Champac, Victor Avendaño, Joan Figueras
2010	B	`conf`	Diagnosis of full open defects in interconnect lines with fan-out. ETS Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2010	B	`conf`	Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. ETS Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras
2009	J	`jnl`	Delay caused by resistive opens in interconnecting lines. Integr. Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
2009	J	`jnl`	Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures. IEEE Trans. Circuits Syst. I Regul. Pap. Luz Balado, Emili Lupon, Joan Figueras, Miquel Roca, Eugeni Isern, Rodrigo Picos
2008	—	`conf`	Data Dependence of Delay Distribution for a Planar Bus. PATMOS Francesc Moll, Joan Figueras, Antonio Rubio
2008	J	`jnl`	Experimental Characterization of CMOS Interconnect Open Defects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
2008	Misc	`conf`	Full Open Defects in Nanometric CMOS. VTS Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2008	A	`conf`	Time-dependent Behaviour of Full Open Defects in Interconnect Lines. ITC Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2007	Misc	`conf`	Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. VTS Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
2007	Misc	`conf`	Diagnosis of Full Open Defects in Interconnecting Lines. VTS Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
2007	J	`jnl`	Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Salvador Manich, Lucas Garcia-Deiros, Joan Figueras
2006	C	`conf`	Lissajous Based Mixed-Signal Testing for N-Observable Signals. DDECS Luz Balado, Emili Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras
2005	B	`conf`	Defective behaviours of resistive opens in interconnect lines. ETS Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras
2005	J	`jnl`	Testing Biquad Filters under Parametric Shifts Using X-Y Zoning. J. Electron. Test. R. Sanahuja, Victor Barcons, Luz Balado, Joan Figueras
2004	J	`jnl`	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. J. Electron. Test. Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras
2004	Misc	`conf`	BIST Technique by Equally Spaced Test Vector Sequences. VTS Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
2004	J	`jnl`	On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electron. Test. Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
2004	B	`conf`	Signal integrity verification using high speed monitors. ETS Victor Avendaño, Víctor H. Champac, Joan Figueras
2003	—	`conf`	On the selection of efficient arithmetic additive test pattern generators [logic test]. ETW Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
2003	—	`conf`	Signal integrity loss in bus lines due to open shielding defects. ETW Victor Avendaño, Víctor H. Champac, Joan Figueras
2003	—	`conf`	Test Engineering Education in Europe: the EuNICE-Test Project. MSE Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden
2002	—	`conf`	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. IOLTW Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras
2002	J	`jnl`	Leakage power bounds in CMOS digital technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Antoni Ferré, Joan Figueras
2002	—	`conf`	On High-Quality, Low Energy BIST Preparation at RT-Level. LATW Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
2002	A	`conf`	RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
2001	J	`jnl`	A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2001	J	`jnl`	Detectability Conditions of Full Opens in the Interconnections. J. Electron. Test. Antonio Zenteno, Víctor H. Champac, Joan Figueras
2001	J	`jnl`	Digital Signature Proposal for Mixed-Signal Circuits. J. Electron. Test. Anna Maria Brosa, Joan Figueras
2001	—	`conf`	Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain. LATW Anotnio Zenteno, Víctor H. Champac, Joan Figueras
2001	J	`jnl`	Guest Editorial. J. Electron. Test. Paolo Prinetto, Joan Figueras
2001	A	`conf`	IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2001	J	`jnl`	LEAP: An Accurate Defect-Free I J. Electron. Test. Antoni Ferré, Joan Figueras
2001	—	`conf`	Test Challenges in a Nanometric World. LATW Joan Figueras
2000	J	`jnl`	An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	—	`conf`	Analyzing the test generation problem for an application-oriented test of FPGAs. ETW Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	Detectability Dependency on Test Generation Process for Interconnection Opens. LATW Antonio Zenteno, Víctor H. Champac, Joan Figueras
2000	A	`conf`	Digital signature proposal for mixed-signal circuits. ITC Anna Maria Brosa, Joan Figueras
2000	—	`conf`	LEAP: An accurate defect-free I ETW Antoni Ferré, Joan Figueras
2000	J	`jnl`	Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
2000	J	`jnl`	On Maximizing the Coverage of Catastrophic and Parametric Faults. J. Electron. Test. Anna Maria Brosa, Joan Figueras
2000	—	`conf`	Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	Test Configuration Generation for FPGA Logic Cells. LATW Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	J	`jnl`	Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	J	`jnl`	Characterization of Floating Gate Defects in Analog Cells. J. Electron. Test. Anna Maria Brosa, Joan Figueras
1999	A	`conf`	Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. DATE Josep Rius, Joan Figueras
1999	J	`jnl`	IDDQ Testing of Opens in CMOS SRAMs. J. Electron. Test. Víctor H. Champac, José Castillejos, Joan Figueras
1999	—	`conf`	Low power BIST by filtering non-detecting vectors. ETW Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
1999	—	`conf`	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
1999	—	`conf`	Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	—	`conf`	On Optimizing Test Strategies for Analog Cells. Great Lakes Symposium on VLSI Anna Maria Brosa, Joan Figueras
1999	—	`conf`	On maximizing the coverage of catastrophic and parametric faults. ETW Anna Maria Brosa, Joan Figueras
1999	J	`jnl`	SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	—	`conf`	Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	A	`conf`	Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	—	`conf`	Characterization of leakage power in CMOS technologies. ICECS Antoni Ferré, Joan Figueras
1998	A	`conf`	Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. DATE Rosa Rodríguez-Montañés, Joan Figueras
1998	Misc	`conf`	IDDQ Testing of Opens in CMOS SRAMs. VTS Víctor H. Champac, José Castillejos, Joan Figueras
1998	J	`jnl`	IDDQ testing: state of the art and future trends. Integr. Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
1998	A	`conf`	Novel Technique for Testing FPGAs. DATE Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
1998	A	`conf`	RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	—	`conf`	SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	B	`conf`	SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	A	`conf`	SRAM-based FPGA's: testing the LUT/RAM modules. ITC Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	J	`jnl`	Testing the Interconnect of RAM-Based FPGAs. IEEE Des. Test Comput. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1997	Misc	`conf`	Bridges in sequential CMOS circuits: current-voltage signatur. VTS Rosa Rodríguez-Montañés, Joan Figueras
1997	J	`jnl`	Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects. VLSI Design Víctor H. Champac, Joan Figueras
1997	J	`jnl`	Fault-Secure Parity Prediction Arithmetic Operators. IEEE Des. Test Comput. Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras
1997	A	`conf`	I ITC Antoni Ferré, Joan Figueras
1997	J	`jnl`	I VLSI Design Eugeni Isern, Joan Figueras
1997	—	`conf`	Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. ED&TC Salvador Manich, Joan Figueras
1997	Misc	`conf`	Power Dissipation During Testing: Should We Worry About it? VTS Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian
1997	—	`conf`	Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1997	Misc	`conf`	Test of RAM-based FPGA: methodology and application to the interconnect. VTS Michel Renovell, Joan Figueras, Yervant Zorian
1996	—	`conf`	Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations. ED&TC Michael Nicolaidis, Salvador Manich, Joan Figueras
1996	J	`jnl`	Bridging defects resistance in the metal layer of a CMOS process. J. Electron. Test. Rosa Rodríguez-Montañés, E. M. J. G. Bruls, Joan Figueras
1996	J	`jnl`	Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. J. Electron. Test. Josep Rius, Joan Figueras
1996	Misc	`conf`	Enhancing realistic fault secureness in parity prediction array arithmetic operators by I VTS Salvador Manich, Michael Nicolaidis, Joan Figueras
1996	Misc	`conf`	On estimating bounds of the quiescent current for I VTS Antoni Ferré, Joan Figueras
1996	—	`conf`	Power Optimization of Delay Constrained CMOS Bus Drivers. ED&TC S. Caufape, Joan Figueras
1995	—	`conf`	A built-in quiescent current monitor for CMOS VLSI circuits. ED&TC Antonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo, P. De Pauw, Jaume Segura
1995	J	`jnl`	Current testing in dynamic CMOS circuits. J. Electron. Test. Joan Figueras, Michel Renovell
1995	Misc	`conf`	Detecting I VTS Josep Rius, Joan Figueras
1995	J	`jnl`	IDDQ Test and Diagnosis of CMOS Circuits. IEEE Des. Test Comput. Eugeni Isern, Joan Figueras
1995	—	`conf`	Synthesis of I ED&TC Hans-Joachim Wunderlich, M. Herzog, Joan Figueras, Juan A. Carrasco, Angel Calderón
1995	Misc	`conf`	Testability of floating gate defects in sequential circuits. VTS Víctor H. Champac, Joan Figueras
1994	—	`conf`	Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability. EDAC-ETC-EUROASIC Rosa Rodríguez-Montañés, Joan Figueras
1994	Misc	`conf`	Analysis of I VTS Eugeni Isern, Joan Figueras
1994	J	`jnl`	Electrical model of the floating gate defect in CMOS ICs: implications on I IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Víctor H. Champac, Antonio Rubio, Joan Figueras
1994	—	`conf`	Test of Bridging Faults in Scan-based Sequential Circuits. EDAC-ETC-EUROASIC Eugeni Isern, Joan Figueras
1993	Misc	`conf`	Analysis of redundant structures in combinational circuits. VTS Eugeni Isern, Joan Figueras
1993	—	`conf`	Analysis of the Floating Gate Defect in CMOS. DFT Víctor H. Champac, Antonio Rubio, Joan Figueras
1993	—	`conf`	Current Testing Viability in Dynamic CMOS Circuits. DFT Michel Renovell, Joan Figueras
1993	A	`conf`	Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits. ITC Eugeni Isern, Joan Figueras
1992	A	`conf`	Bridging Defects Resistance Measurements in a CMOS Process. ITC Rosa Rodríguez-Montañés, Joan Figueras, Eric Bruls
1992	J	`jnl`	Proportional BIC sensor for current testing. J. Electron. Test. Josep Rius, Joan Figueras
1992	J	`jnl`	Quiescent current analysis and experimentation of defective CMOS circuits. J. Electron. Test. Jaume A. Segura, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio
1991	A	`conf`	Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. ITC Rosa Rodríguez-Montañés, Jaume A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio
1991	J	`jnl`	Evaluation of safety-oriented two-version architectures. J. Syst. Softw. Juan A. Carrasco, Joan Figueras, Annie Kuntzmann-Combelles