Joakim Urdahl

14 papers A* 1A 2B 1C 1Misc 1Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2020 J jnl
Properties First - Correct-By-Construction RTL Design in System-Level Design Flows.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tobias Ludwig, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2019 J jnl
Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows.
IEEE Trans. Very Large Scale Integr. Syst.
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2018 A conf
Symbolic quick error detection using symbolic initial state for pre-silicon verification.
DATE
Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivasa Shashank Nuthakki, Subhasish Mitra, Clark W. Barrett, Dominik Stoffel, Wolfgang Kunz
2017 Misc conf
Dynamic Power Optimization Based on Formal Property Checking of Operations.
VLSID
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2017 — conf
Dynamic Power Optimization based on Formal Property Checking of Operations.
MBMV
Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2016 — —
Path Predicate Abstraction: for Sound System-Level Modeling of Digital Circuits.
Joakim Urdahl
2016 A conf
Properties first? a new design methodology for hardware, and its perspectives in safety analysis.
ICCAD
Joakim Urdahl, Shrinidhi Udupi, Tobias Ludwig, Dominik Stoffel, Wolfgang Kunz
2015 — conf
Architectural System Modeling for Correct-by-Construction RTL Design.
MBMV
Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2015 C conf
Architectural system modeling for correct-by-construction RTL design.
FDL
Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2014 J jnl
Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz
2014 — conf
T4B: Formal verification in system-on-chip design: Scientific foundations and practical methodology.
SoCC
Wolfgang Kunz, Dominik Stoffel, Joakim Urdahl
2013 — conf
Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design.
PATMOS
Joakim Urdahl, Shrinidhi Udupi, Dominik Stoffel, Wolfgang Kunz
2012 A* conf
System verification of concurrent RTL modules by compositional path predicate abstraction.
DAC
Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz
2010 B conf
Path predicate abstraction by complete interval property checking.
FMCAD
Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, Wolfgang Kunz